AI FAE Platform2. Product and Kit Overview
The N32H49x series is a family of high-performance MCUs from Nations Technologies built on a 32-bit Arm Cortex-M4F core running at up to 240 MHz, integrating a trigonometric accelerator, a delta-sigma digital demodulation module, Ethernet, USB, and multiple CAN-FD interfaces for industrial control, energy storage, optical communications, and power and fire-safety applications.
2.1 Core and Peripheral Overview
The table below gives the maximum configuration of the three sub-series. The core and bus data come from the “Memory and bus architecture” chapter of the user manual, the memory sizes from the “FLASH specifications” section of the user manual and the official model pages, and the remaining peripheral items are summarized from the peripheral chapters of the user manual and the SDK example categories.
| Item | N32H492 | N32H493 | N32H497 |
|---|---|---|---|
| Core | Arm Cortex-M4F with single-precision FPU and DSP instructions; MPU, 8 KB I-Cache, and 1 KB D-Cache |
Same as N32H492 | Same as N32H492 |
| Max frequency | 240 MHz | 240 MHz | 240 MHz |
| Bus clock limits | HCLK 240 MHz; PCLK1 120 MHz; PCLK2 120 MHz |
Same as N32H492 | Same as N32H492 |
| Memory | Dual-bank encrypted Flash up to 1 MB; SRAM up to 320 KB (including 80 KB CCM) plus 4 KB backup |
Dual-bank encrypted Flash up to 1 MB | Dual-bank encrypted Flash up to 1 MB; SRAM up to 576 KB (including 80 KB CCM) plus 4 KB backup |
| GPIO | 64 to 144-pin packages depending on the part | As provided by the part | Up to 118 |
| Analog | 3 x 12-bit 4.7 Msps ADC, 2 x 12-bit DAC, VREFBUF | Same as N32H492 | Same as N32H492 |
| Communication | 3 x CAN-FD, 10 x U(S)ART, 6 x SPI, 4 x I2C, 2 x I2S, USB FS device, USB HS host/device, Ethernet MAC, SDIO, DVP | Same as N32H492, plus an independent low-voltage I/O domain | Same as N32H492 |
| Timers | ATIM, GTIM, BTIM, LPTIM, IWDG, WWDG | Same as N32H492 | Same as N32H492 |
| Other peripherals | CORDIC trigonometric accelerator, DSMU delta-sigma demodulation, DMA1/DMA2, FEMC, xSPI, SDRAM, CRC | Same as N32H492 | Same as N32H492 |
| Reset and supply monitoring | Power-on, power-down, and external pin reset; programmable voltage detector (PVD); watchdog reset |
Same as N32H492 | Same as N32H492 |
| Debug and boot | SWD debug; boot from main Flash, system memory, or internal SRAM, with XSPI, FEMC, and SDRAM remap boot |
Same as N32H492 | Same as N32H492 |
| Security and identification | Hardware crypto engine (AES, DES/3DES, SHA, SM3, SM4, MD5), TRNG, SMPU, read and write protection, 96-bit UID and 128-bit UCID | Same as N32H492 | Same as N32H492 |
| Operating conditions | 1.8 V to 3.6 V, -40 degC to +105 degC | Same as N32H492 | Same as N32H492 |
The table gives the maximum configuration of the sub-series. Refer to the datasheet of each part for its Flash, SRAM, and GPIO count and for peripheral cuts. N32H497 and N32H492 differ in SRAM size, and the independent low-voltage I/O domain is specific to N32H493.
2.2 SDK at a Glance
Nsing.N32H49x_Library.1.2.0 consists of CMSIS device support files, the standard peripheral driver library, middleware, and evaluation board projects. Its scale is as follows:
- 30 driver modules
- 1256 public APIs
- 34 example categories
- 184 examples
| Component | Content |
|---|---|
| Standard peripheral driver library | Each driver module is a pair of .h / .c files;the public API is every function declared in the header |
| CMSIS device support | Device header, system clock initialization, Keil / IAR / GCC startup files, and a GCC linker script |
| Algorithm library | AES, DES, HASH, RNG, SM4, and common functions, provided as both Keil .lib and GCC .a |
| USB drivers | Full-speed device driver (USBFSD) and high-speed host/device driver (USBHS) |
| Middleware | FatFs file system, FreeRTOS kernel, and the lwIP stack |
| Example projects | Organized by peripheral category; each example provides both a Keil MDK-ARM and an IAR EWARM project |
| Application project | GCC_demo (a GCC Makefile project) |
| Board support | LED, key, and USB VBUS pin definitions, log UART output, and SysTick delay |
Examples are counted as entries that contain an MDK-ARM, EWARM, or GCC build project: paired sub-projects whose readme sits only in the parent directory count as one, sub-projects that each carry their own readme count separately, and shared code directories without a project do not count. The ALGO, Cortex-M4F, USBFSD, and USBHS categories do not use the standard peripheral drivers under n32h49x_std_periph_driver/, and the DBG driver module has no standalone example; I2S and SPI share n32h49x_spi.h, XSPI_V2 corresponds to n32h49x_xspi_v2.h, and the NVIC category corresponds to misc.h.
The default system clock source in system_n32h49x.c is HSI through the PLL, with SYSCLK_FREQ defaulting to 240000000 for a 240 MHz output. Change it before the build through the SYSCLK_FREQ and SYSCLK_SRC macros; the PLL multiplier must be between 8 and 76 and even, otherwise system_n32h49x.c stops the build with an error.