5.32 WWDG Guide

This chapter describes the file composition and 8 public functions of the WWDG driver in the N32H49x standard peripheral library, together with the WWDG_Reset example. The WWDG is a 14-bit window watchdog clocked from the APB1 clock, where the counter may only be refreshed while its value falls inside the refresh window, and refreshing too early or too late triggers a reset; for the window value and refresh window calculation, see the “Window watchdog (WWDG)” chapter of the user manual.

5.32.1 Related files

Relative path Purpose
firmware/n32h49x_std_periph_driver/inc/n32h49x_wwdg.h Defines the prescaler and working mode parameters, and declares the 8 public functions
firmware/n32h49x_std_periph_driver/src/n32h49x_wwdg.c Implements the 8 functions above: register reset, writing the prescaler, window value and counter value, enable and interrupt, and reading and clearing the early wakeup interrupt flag
projects/n32h49x_EVAL/examples/WWDG/ WWDG example root directory, containing the single WWDG_Reset example
projects/n32h49x_EVAL/examples/WWDG/WWDG_Reset/ Project directory composition of this example: MDK-ARM/, EWARM/, inc/, src/, readme.txt
projects/n32h49x_EVAL/bsp/ Common board files referenced by this example: the UART log and millisecond delay functions

5.32.2 API reference

Search API8 functions

The following 8 public functions are listed in the declaration order of n32h49x_wwdg.h in 3 groups; each entry gives a summary and the original comment above the function in n32h49x_wwdg.c.

Reset and configuration

WWDG_DeInit, WWDG_SetPrescalerDiv, WWDG_SetWValue

Count and enable

WWDG_EnableInt, WWDG_SetCnt, WWDG_Enable

Flag status

WWDG_GetEWINTF, WWDG_ClrEWINTF

void WWDG_DeInit(void)Resets the WWDG peripheral registers to their default reset values.
Source comment
name    WWDG_DeInit.
fun     Resets the WWDG peripheral registers to their default reset values.
return  none
void WWDG_SetPrescalerDiv(uint32_t WWDG_Prescaler)Set the WWDOG Prescaler Division Value.
Source comment
name    WWDG_SetPrescalerDiv.
fun     Set the WWDOG Prescaler Division Value.
param   WWDG_Prescaler :
          - WWDG_PRESCALER_DIV1   WWDG Counter Clock (PCLK1 / 4096) / 1
          - WWDG_PRESCALER_DIV2   WWDG Counter Clock (PCLK1 / 4096) / 2
          - WWDG_PRESCALER_DIV4   WWDG Counter Clock (PCLK1 / 4096) / 4
          - WWDG_PRESCALER_DIV8   WWDG Counter Clock (PCLK1 / 4096) / 8
return  none
void WWDG_SetWValue(uint16_t WindowValue)Set the WWDOG Window Value.
Source comment
name    WWDG_SetWValue.
fun     Set the WWDOG Window Value.
param   WindowValue : WWDOG Window Value
          The value range of this parameter :
          - 0x0040 ~ 0x3FFF
return  none
void WWDG_EnableInt(void)Enable WWDG Early Wakeup interrupt(EWINT).
Source comment
name    WWDG_EnableInt.
fun     Enable WWDG Early Wakeup interrupt(EWINT).
return  none
void WWDG_SetCnt(uint16_t Counter)Set the WWDOG Counter Value.
Source comment
name    WWDG_SetCnt.
fun     Set the WWDOG Counter Value.
param   Counter : WWDOG Counter value
          The value range of this parameter :
          - 0x40 ~ 0x3FFF
return  none
void WWDG_Enable(uint16_t Counter)Set the WWDOG Counter Value and Enable WWDOG .
Source comment
name    WWDG_Enable.
fun     Set the WWDOG Counter Value and Enable WWDOG .
param   Counter : WWDOG Counter value
          The value range of this parameter :
          - 0x40 ~ 0x3FFF
return  none

Use note: The implementation writes WWDG->CTRL = CTRL_ACTB_SET | Counter, setting the activation bit and writing the 14-bit counter value at the same time.

FlagStatus WWDG_GetEWINTF(void)Get WWDOG Early Wake-up Interrupt Flag.
Source comment
name    WWDG_GetEWINTF.
fun     Get WWDOG Early Wake-up Interrupt Flag.
param   none
return  SET or RESET
void WWDG_ClrEWINTF(void)Clear WWDOG Early Wake-up Interrupt Flag.
Source comment
name    WWDG_ClrEWINTF.
fun     Clear WWDOG Early Wake-up Interrupt Flag.
return  none

Use note: The implementation writes RESET (0) to WWDG->STS to clear the early wakeup interrupt flag.

5.32.3 Demo descriptions

This section describes the single WWDG example: WWDG_Reset configures the refresh window and refreshes the counter periodically in the main loop to demonstrate a WWDG reset triggered by refreshing too early or too late.

5.32.3.1 WWDG_Reset WWDG reset

Example directory: projects/n32h49x_EVAL/examples/WWDG/WWDG_Reset/

Initialize the UART log and the indicators and clear the early wakeup interrupt flag→Check whether the last reset was caused by the WWDG and light LED1→Delay 1 second to avoid download difficulty caused by frequent resets→Configure the prescaler, window value and counter value and start the WWDG→Toggle LED3 and refresh the counter after a delay in the main loop

Item Source analysis
Function Configures the WWDG counter clock to PCLK1/4096/8 with a window value of 80 and an initial counter value of 127;
the main loop refreshes the counter every 16 ms, LED3 keeps blinking during normal operation, refreshing too early or too late triggers a WWDG reset, after which LED1 lights up and reset by WWDG is printed on the UART.
Source files src/main.c: main together with LedInit, LedOn, LedOff, LedBlink;
inc/main.h: includes n32h49x_wwdg.h, n32h49x_rcc.h, n32h49x_gpio.h, delay.h, log.h;
src/n32h49x_it.c, inc/n32h49x_it.h: interrupt service routines;
readme.txt: function, environment and usage notes;
MDK-ARM/, EWARM/: Keil and IAR projects.
Key configuration Clock: RCC_EnableAPB1PeriphClk enables the WWDG and PWR clocks with prescaler WWDG_PRESCALER_DIV8;
Window and counter: WWDG_SetWValue(80) and WWDG_Enable(127), and a refresh must land the counter value between 64 and 80;
Indicators: LED1 is PA3 and LED3 is PA8, push-pull output;
a 1 second delay before enabling avoids download problems caused by frequent resets.
Program and data path main calls log_init, clears the early wakeup interrupt flag with WWDG_ClrEWINTF, initializes and turns off LED1 and LED3, then enables the PWR clock;
checks RCC_FLAG_WWDGRSTF: when set it lights LED1, prints reset by WWDG and clears the reset flags, otherwise it turns off LED1;
after a 1 second delay it enables the WWDG clock and configures the prescaler, window value and counter value;
while(1) toggles PA8 (LED3), waits 16 ms and then refreshes the counter with WWDG_SetCnt(127).
Main APIs WWDG_SetPrescalerDiv, WWDG_SetWValue, WWDG_Enable, WWDG_SetCnt, WWDG_ClrEWINTF
Verification After building, downloading and resetting, LED3 toggles about every 16 ms and blinks continuously, showing that the refresh lands inside the window;
change the systick_delay_ms argument to outside the window range (too small or too large), and the system will keep resetting, LED1 lights up and the UART prints reset by WWDG.
Use note The hardware development environment is the full-featured board N32H497ZGL7_EVB V1.0;
the development environment is KEIL MDK-ARM 5.34 or IAR EWARM 8.50.1;
when the window value is very small the system may reset frequently and the program cannot be downloaded normally, so the example adds a 1 second delay before enabling the WWDG, and alternatively the BOOT0 pin can be pulled high during download.
Core-code walkthrough and porting

The example first clears the early wakeup interrupt flag and checks whether the last reset came from the WWDG, delays 1 second in advance to avoid download problems, then configures and starts the WWDG, and finally refreshes the counter in the main loop.

Data path: WWDG_ClrEWINTF clears the flag → RCC_FLAG_WWDGRSTF reset flag → WWDG_SetPrescalerDiv, WWDG_SetWValue, WWDG_Enable write the WWDG registers → the main loop WWDG_SetCnt refreshes the counter → LED3 toggles and LED1 lights up on a reset

1. Initialize the log, the indicators and the interrupt flag. main first calls log_init, clears the early wakeup interrupt flag, initializes LED1 (PA3) and LED3 (PA8) as push-pull outputs and turns them off, then enables the PWR clock.

src/main.csrc/main.c · main
    log_init();
    log_info("--- WWDG demo reset ---\n");
    WWDG_ClrEWINTF();
    LedInit(GPIOA, LED1 | LED3);
    LedOff(GPIOA, LED1 | LED3);
    /* Enable PWR Clock */
    RCC_EnableAPB1PeriphClk(RCC_APB1_PERIPHEN_PWR, ENABLE);

When porting to another board, only the LED1 and LED3 pin macros need to change; WWDG_ClrEWINTF must be called before enabling the WWDG to avoid a leftover flag from the previous run.

2. Check the reset source and display it. RCC_FLAG_WWDGRSTF is read: if this reset was caused by the WWDG, LED1 lights up, a message is printed and the reset flags are cleared, otherwise LED1 is turned off.

src/main.csrc/main.c · main
    /* Check if the system has resumed from WWDG reset */
    if (RCC_GetFlagStatus(RCC_FLAG_WWDGRSTF) != RESET)
    {
        /* WWDGRST flag set */
        /* Turn on LED1 */
        LedOn(GPIOA, LED1);
        log_info("reset by WWDG\n");
        /* Clear reset flags */
        RCC_ClearResetFlag();
    }
    else
    {
        /* WWDGRST flag is not set */
        /* Turn off LED1 */
        LedOff(GPIOA, LED1);
    }

When porting, keep the reset flag clear call, otherwise the next power-up still reads a stale reset source.

3. Delay 1 second before enabling. When the window value is very small the system may be in a frequent reset state, which prevents the program from being downloaded normally; the example delays 1 second here to avoid that.

src/main.csrc/main.c · main
    /*
      When the window value is very small, the system is in a frequent reset state,
      at this time, easy to cause the program can not download normally.
      Add a delay of 1 second here to avoid this phenomenon. Of course,
      it can also be downloaded without delay, directly pull the pin of BOOT0 high.
    */
    systick_delay_ms(1000);

When porting, the delay can be shortened to reduce the power-on wait, but the program must still be downloadable.

4. Configure and start the WWDG. After enabling the WWDG clock, the prescaler, window value and counter value are written in turn, and WWDG_Enable starts the counter while writing the counter value.

src/main.csrc/main.c · main
    /* WWDG configuration */
    /* Enable WWDG clock */
    RCC_EnableAPB1PeriphClk(RCC_APB1_PERIPHEN_WWDG, ENABLE);

    /* WWDG clock counter = 1/((PCLK1(120MHz)/4096)/8) = (~273 us)  */
    /* WWDG clock counter = 1/((PCLK1(100MHz)/4096)/8) = (~327 us)  */
    WWDG_SetPrescalerDiv(WWDG_PRESCALER_DIV8);

    /* Set Window value to 80; WWDG counter should be refreshed only when the counter
      is below 80 (and greater than 64) otherwise a reset will be generated */
    WWDG_SetWValue(80);

    /*
      When PCLK1 = 120MHz, in this case the refresh window is: ~273 us * (127-80) = 12.831 ms < refresh window < ~273 us * (127-63) = 17.472ms
      When PCLK1 = 100MHz, in this case the refresh window is: ~327 us * (127-80) = 15.401 ms < refresh window < ~327 us * (127-63) = 20.971ms
    */
    WWDG_Enable(127);

The refresh window is determined jointly by the prescaler, the window value and the current counter value, so changing any one of them requires checking the window range again.

5. Refresh the counter in the main loop. The loop toggles LED3, waits 16 ms and then refreshes the counter with WWDG_SetCnt(127).

src/main.csrc/main.c · main
    while (1)
    {
        /* Toggle LED3 */
        LedBlink(GPIOA, LED3);
        systick_delay_ms(16);
        /* Update WWDG counter */
        WWDG_SetCnt(127);
    }

The 16 ms delay falls inside the refresh window of the example; moving it outside the window triggers a WWDG reset.

Corresponding source files: src/main.c

5.32.4 Notes and troubleshooting

Scenario Check & action Source
Refresh window The counter must be refreshed before it decrements to 0x40 (that is, while the counter is still greater than 0x3F), otherwise a reset is generated. User manual
Window value constraint A refresh is only allowed while the counter value is smaller than the window value;
the window value is written to WWDG_CFG.W[13:0], and at least one bit of T[13:6] must be 1, so the window value is not less than 0x40.
User manual
Counter initial value The counter initial value must be greater than 0x3F and not greater than the window value, otherwise the refresh window condition is not met at start-up. User manual
Early wakeup interrupt flag The early wakeup interrupt flag EWINTF is cleared by writing 0;
refreshing the counter inside the early wakeup interrupt avoids a reset, but the refresh must still meet the window condition.
User manual
Stopping in debug mode Whether the WWDG is frozen when the core is halted in debug is determined by the DBG_CTRL.WWDG_STOP bit of the debug module. User manual
Clock source The WWDG counter clock comes from PCLK1, divided by a fixed 4096 and then by the prescaler factor;
the APB1 clock of the WWDG must be enabled before enabling the WWDG.
User manual
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