5.18 IWDG Guide

The example first detects whether this reset came from the IWDG, then performs write access, prescaler, reload and start in turn, and finally feeds the watchdog periodically in the main loop.

Data path: RCC_FLAG_IWDGRSTF reset flag → IWDG_WriteConfig, IWDG_SetPrescalerDiv, IWDG_CntReload, IWDG_Enable write IWDG_PREDIV, IWDG_RELV and IWDG_KEY → the main loop IWDG_ReloadKey reloads the counter → LED3 toggles and LED1 lights up on a reset

1. Initialize and turn on the indicators. main first calls log_init, initializes LED1 (PA3) and LED3 (PA8) as push-pull outputs and turns them off.

    log_init();
    log_info("--- IWDG demo reset ---\n");
    LedInit(LED1_GPIO_PORT, LED1_GPIO_PIN);
    LedInit(LED3_GPIO_PORT, LED3_GPIO_PIN);
    LedOff(LED1_GPIO_PORT, LED1_GPIO_PIN);
    LedOff(LED3_GPIO_PORT, LED3_GPIO_PIN);

When porting to another board, only the LED1_GPIO_PORT, LED1_GPIO_PIN, LED3_GPIO_PORT and LED3_GPIO_PIN macros need to change; the LED initialization is unrelated to the IWDG itself.

2. Check the reset source and display it. PWR clock is enabled first, then RCC_FLAG_IWDGRSTF is read: if this reset was caused by the IWDG, LED1 lights up, a message is printed and the reset flags are cleared, otherwise LED1 is turned off.

    /* Check if the system has resumed from IWDG reset */
    if(RCC_GetFlagStatus(RCC_FLAG_IWDGRSTF) != RESET)
    {
        /* IWDGRST flag set */
        /* Turn on LED1 */
        LedOn(LED1_GPIO_PORT, LED1_GPIO_PIN);
        log_info("reset by IWDG\n");
        /* Clear reset flags */
        RCC_ClearResetFlag();
    }
    else
    {
        /* IWDGRST flag is not set */
        /* Turn off LED1 */
        LedOff(LED1_GPIO_PORT, LED1_GPIO_PIN);
    }

When porting, keep the reset flag clear call, otherwise the next power-up still reads a stale reset source; the PWR clock must be enabled before reading this flag.

3. Configure and start the IWDG. main opens write access, writes the prescaler and reload values, then reloads and starts the counter.

    /* IWDG timeout equal to 250 ms (the timeout may varies due to LSI frequency
       dispersion) */
    /* Enable write access to IWDG_PR and IWDG_RLR registers */
    IWDG_WriteConfig(IWDG_WRITE_ENABLE);

    /* IWDG counter clock: LSI/32 */
    IWDG_SetPrescalerDiv(IWDG_PRESCALER_DIV32);

    /* Set counter reload value to obtain 250ms IWDG TimeOut.
       Counter Reload Value = 250ms/IWDG counter clock period
                            = 250ms / (LSI/128)
                            = 0.25s / (LsiFreq/32)
                            = LsiFreq/(32 * 4)
                            = LsiFreq/128 */
    log_debug("LsiFreq is: %d\n", LsiFreq);

    IWDG_CntReload(LsiFreq / 128);
    /* Reload IWDG counter */
    IWDG_ReloadKey();

    /* Enable IWDG (the LSI oscillator will be enabled by hardware) */
    IWDG_Enable();

LsiFreq defaults to 32000 Hz, which with prescaler IWDG_PRESCALER_DIV32 gives a timeout of about 250 ms; when changing the timeout, check the prescaler factor and the IWDG_CntReload argument together.

4. Feed the watchdog periodically in the main loop. The loop toggles LED3, waits 249 ms and then reloads the counter with IWDG_ReloadKey.

    while(1)
    {
        /* Toggle LED3 */
        LedBlink(LED3_GPIO_PORT, LED3_GPIO_PIN);
        /* Insert 249 ms delay */
        systick_delay_ms(249);
        /* Reload IWDG counter */
        IWDG_ReloadKey();
    }

The feed interval must be shorter than the timeout (here 249 ms is less than 250 ms); changing the delay beyond the timeout triggers an IWDG reset.

Corresponding source files: src/main.c