AI FAE Platform5.27 TIM Guide
This chapter covers the files of the TIM driver (n32h49x_tim.h / n32h49x_tim.c) in the N32H49x standard peripheral library, its 153 public functions, and the 21 TIM examples. It covers reset and initialization of the advanced timers ATIM, general-purpose timers GTIM, and basic timers BTIM, clock sources and slave mode, output compare and PWM, input capture and PWM input, break and dead time, DMA transfer, the encoder interface, and master/slave timer synchronization. Read it together with chapters 9 to 13 of the user manual for the register bit definitions, the time-base unit, external clocks and the encoder interface, and break and output modes.
5.27.1 Related files
| Relative path | Purpose |
|---|---|
firmware/n32h49x_std_periph_driver/inc/n32h49x_tim.h |
Defines structures such as TIM_TimeBaseInitType, OCInitType, TIM_ICInitType, TIM_BDTRInitType, and TIM_FiltInitType, and macros for the counter mode, clock division, output compare mode, input capture selection, break source, and trigger source;declares the 153 public functions in sections (reset and initialization, channel initialization, break, clock and slave mode, output, input, interrupt) |
firmware/n32h49x_std_periph_driver/src/n32h49x_tim.c |
Implements the 153 functions: time base and channel initialization, clock source and slave mode, output compare and PWM, input capture and PWM input, break and dead time, DMA and burst transfer, interrupt and flag status |
projects/n32h49x_EVAL/examples/TIM/ |
TIM example root, containing the 21 examples: TimeBase, TimeBasic_ATIM1/BTIM1/GTIM2/GTIM8, 6Steps, PWM_Output, PWM_Input, ComplementarySignals, ATIM1_Synchro, Cascade_Synchro, Parallel_Synchro, ExtTrigger_Synchro, OCActive, OCInactive, OCToggle, OnePulse, InputCapture, DMA, DMABurst, Quadrature_Output |
projects/n32h49x_EVAL/examples/TIM/TimeBase/ |
Project layout of that example: MDK-ARM/, EWARM/, inc/, src/, readme.txt |
firmware/CMSIS/device/n32h49x.h |
Device register and peripheral instance definitions, referenced indirectly by each example through inc/main.h |
5.27.2 API reference
The 153 public functions below follow the declaration order of n32h49x_tim.h and fall into 19 groups; each entry gives a summary and the original comment directly above the function in n32h49x_tim.c.
Reset and initialization
TIM_DeInit, TIM_InitTimeBase, TIM_InitOc1, TIM_InitOc2, TIM_InitOc3, TIM_InitOc4, TIM_InitOc5, TIM_InitOc6
Input capture and PWM input initialization
TIM_ICInit, TIM_ConfigPwmIc
Break and dead-time configuration
TIM_ConfigBkdt, TIM_BreakFiltConfig, TIM_BreakFiltEnable, TIM_Break2FiltEnable, TIM_Break2FiltConfig, TIM_BreakInputSourceEnable, TIM_Break2InputSourceEnable, TIM_BidirectionDisarm, TIM_BidirectionRearm, TIM_Bidirection2Disarm, TIM_Bidirection2Rearm
Structure defaults
TIM_InitTimBaseStruct, TIM_InitOcStruct, TIM_InitIcStruct, TIM_InitBkdtStruct
Enable, interrupt, DMA, and events
TIM_Enable, TIM_EnableCtrlPwmOutputs, TIM_ConfigInt, TIM_GenerateEvent, TIM_ConfigDma, TIM_EnableDma
Clock source and slave mode
TIM_ConfigInternalClk, TIM_ConfigInternalTrigToExt, TIM_ConfigExtTrigAsClk, TIM_ConfigExtClkMode1, TIM_ConfigExtClkMode2, TIM_ConfigPrescaler, TIM_ConfigCntMode, TIM_ConfigEncoderInterface
Forced output and auto-reload preload
TIM_ConfigForcedOc1, TIM_ConfigForcedOc2, TIM_ConfigForcedOc3, TIM_ConfigForcedOc4, TIM_ConfigForcedOc5, TIM_ConfigForcedOc6, TIM_ConfigArPreload
Commutation event, capture/compare DMA, and preload control
TIM_SelectComEvt, TIM_SelectCapCmpDmaSrc, TIM_EnableCapCmpPreloadControl
Output compare preload
TIM_ConfigOc1Preload, TIM_ConfigOc2Preload, TIM_ConfigOc3Preload, TIM_ConfigOc4Preload, TIM_ConfigOc5Preload, TIM_ConfigOc6Preload, TIM_ConfigOc7Preload, TIM_ConfigOc8Preload, TIM_ConfigOc9Preload
Output compare fast enable
TIM_ConfigOc1Fast, TIM_ConfigOc2Fast, TIM_ConfigOc3Fast, TIM_ConfigOc4Fast, TIM_ConfigOc5Fast, TIM_ConfigOc6Fast
OCREF clear
TIM_ClrOc1Ref, TIM_ClrOc2Ref, TIM_ClrOc3Ref, TIM_ClrOc4Ref, TIM_ClrOc5Ref, TIM_ClrOc6Ref, TIM_ClrOcRefInputSource
Output polarity
TIM_ConfigOc1Polarity, TIM_ConfigOc1NPolarity, TIM_ConfigOc2Polarity, TIM_ConfigOc2NPolarity, TIM_ConfigOc3Polarity, TIM_ConfigOc3NPolarity, TIM_ConfigOc4Polarity, TIM_ConfigOc4NPolarity, TIM_ConfigOc5Polarity, TIM_ConfigOc6Polarity
Channel enable and output compare mode
TIM_EnableCapCmpCh, TIM_EnableCapCmpChN, TIM_SelectOcMode, TIM_EnableUpdateEvt
Update event, one-pulse, slave mode, and master/slave mode
TIM_ConfigUpdateEvt, TIM_ConfigUpdateRequestIntSrc, TIM_SelectHallSensor, TIM_SelectOnePulseMode, TIM_SelectOutputTrig, TIM_SelectOutputTrig2, TIM_SelectSlaveMode, TIM_SelectMasterSlaveMode
Counter and compare value setting
TIM_SetCnt, TIM_SetAutoReload, TIM_SetCmp1, TIM_SetCmp2, TIM_SetCmp3, TIM_SetCmp4, TIM_SetCmp5, TIM_SetCmp6, TIM_SetCmp7, TIM_SetCmp8, TIM_SetCmp9, TIM_SetCmp1D, TIM_SetCmp2D, TIM_SetCmp3D, TIM_SetCmp4D
Input channel, input capture prescaler, and trigger configuration
ConfigTI1, ConfigTI2, ConfigTI3, ConfigTI4, TIM_SetInCap1Prescaler, TIM_SetInCap2Prescaler, TIM_SetInCap3Prescaler, TIM_SetInCap4Prescaler, TIM_SelectInputTrig, TIM_ConfigExtTrig, TIM_SelectETRInputSource, TIM_SetClkDiv
Capture value read
TIM_GetCap1, TIM_GetCap2, TIM_GetCap3, TIM_GetCap4, TIM_GetCap5, TIM_GetCap6, TIM_GetCap7, TIM_GetCap8, TIM_GetCap9, TIM_GetCap1D, TIM_GetCap2D, TIM_GetCap3D, TIM_GetCap4D
Counter and status read
TIM_GetCnt, TIM_GetPrescaler, TIM_GetAutoReload, TIM_GetCCENStatus, TIM_GetFlagStatus, TIM_ClearFlag, TIM_GetIntStatus, TIM_ClrIntPendingBit
Center-aligned, asymmetric, ADC trigger, and channel filter
TIM_SelectCenterAlignTrig, TIM_AsymmetricEnable, TIM_OCxRefTriggerADC, TIM_IC1FiltConfig, TIM_IC2FiltConfig, TIM_IC3FiltConfig, TIM_IC4FiltConfig, TIM_IC1FiltEnable, TIM_IC2FiltEnable, TIM_IC3FiltEnable, TIM_IC4FiltEnable, TIM_GetFiltStatus
void TIM_DeInit(TIM_Module* TIMx)Deinitializes the TIMx registers.
Source comment
name TIM_DeInit
fun Deinitializes the TIMx registers.
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
- ATIM3
- GTIM1
- GTIM2
- GTIM3
- GTIM4
- GTIM5
- GTIM6
- GTIM7
- GTIM8
- GTIM9
- GTIM10
- BTIM1
- BTIM2
return none
void TIM_InitTimeBase(TIM_Module* TIMx, TIM_TimeBaseInitType* TIM_TimeBaseInitStruct)Initializes the TIMx time base unit.
Source comment
name TIM_InitTimeBase
fun Initializes the TIMx time base unit.
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
- ATIM3
- GTIM1
- GTIM2
- GTIM3
- GTIM4
- GTIM5
- GTIM6
- GTIM7
- GTIM8
- GTIM9
- GTIM10
- BTIM1
- BTIM2
param TIM_TimeBaseInitStruct: refer to the definition of TIM_TimeBaseInitType
- Prescaler
* 0x0000 ~ 0xFFFF
- CounterMode
* TIM_CNT_MODE_UP
* TIM_CNT_MODE_DOWN
* TIM_CNT_MODE_CENTER_ALIGN1
* TIM_CNT_MODE_CENTER_ALIGN2
* TIM_CNT_MODE_CENTER_ALIGN3
- Period
* GTIM1 and GTIM4 range from 0x00000000 to 0xffffffff, but the others range from 0x0000 to 0xffff.
- ClkDiv
* TIM_CLK_DIV1
* TIM_CLK_DIV2
* TIM_CLK_DIV4
- RepetCnt
* 0x00 ~ 0xFF
- CapCh1Sel
* TIM_CAPCH1SEL_0
* TIM_CAPCH1SEL_5
* TIM_CAPCH1SEL_6
* TIM_CAPCH1SEL_7
- CapCh2Sel
* TIM_CAPCH2SEL_0
* TIM_CAPCH2SEL_1
* TIM_CAPCH2SEL_4
* TIM_CAPCH2SEL_TIMXCAPLSE
- CapCh3Sel
* TIM_CAPCH3SEL_0
* TIM_CAPCH3SEL_1
* TIM_CAPCH3SEL_TIMXCAPLSI
- CapCh4Sel
* TIM_CAPCH4SEL_0
* TIM_CAPCH4SEL_1
* TIM_CAPCH4SEL_2
* TIM_CAPCH4SEL_TIMXCAPHSEDIV128
- EtrOrClr
* TIM_ETRSEL
* TIM_CLRSEL
- CapEtrClrSel
* TIM_CAPETRSEL_0
* TIM_CAPETRSEL_8
* TIM_CAPETRSEL_10
* TIM_CAPETRSEL_11
* TIM_CAPETRSEL_12
* TIM_CAPETRSEL_13
return none
void TIM_InitOc1(TIM_Module* TIMx, OCInitType* TIM_OCInitStruct)Initializes the TIMx Channel 1.
Source comment
name TIM_InitOc1
fun Initializes the TIMx Channel 1.
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
- ATIM3
- GTIM1
- GTIM2
- GTIM3
- GTIM4
- GTIM5
- GTIM6
- GTIM7
- GTIM8
- GTIM9
- GTIM10
param TIM_OCInitStruct: refer to the definition of OCInitType
- OCMode
* TIM_OCMODE_TIMING
* TIM_OCMODE_ACTIVE
* TIM_OCMODE_INACTIVE
* TIM_OCMODE_TOGGLE
* TIM_FORCED_ACTION_INACTIVE
* TIM_FORCED_ACTION_ACTIVE
* TIM_OCMODE_PWM1
* TIM_OCMODE_PWM2
* TIM_OCMODE_OPMOD_RETRIG1
* TIM_OCMODE_OPMOD_RETRIG2
* TIM_OCMODE_COMBI_PWM1
* TIM_OCMODE_COMBI_PWM2
- OutputState
* TIM_OUTPUT_STATE_DISABLE
* TIM_OUTPUT_STATE_ENABLE
- OutputNState
* TIM_OUTPUT_NSTATE_DISABLE
* TIM_OUTPUT_NSTATE_ENABLE
- Pulse
* GTIM1 and GTIM4 range from 0x00000000 to 0xffffffff, but the others range from 0x0000 to 0xffff.
- OCPolarity
* TIM_OC_POLARITY_HIGH
* TIM_OC_POLARITY_LOW
- OCNPolarity
* TIM_OCN_POLARITY_HIGH
* TIM_OCN_POLARITY_LOW
- OCIdleState
* TIM_OC_IDLE_STATE_SET
* TIM_OC_IDLE_STATE_RESET
- OCNIdleState
* TIM_OCN_IDLE_STATE_SET
* TIM_OCN_IDLE_STATE_RESET
return none
void TIM_InitOc2(TIM_Module* TIMx, OCInitType* TIM_OCInitStruct)Initializes the TIMx Channel 2.
Source comment
name TIM_InitOc2
fun Initializes the TIMx Channel 2.
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
- ATIM3
- GTIM1
- GTIM2
- GTIM3
- GTIM4
- GTIM5
- GTIM6
- GTIM7
- GTIM8
- GTIM9
- GTIM10
param TIM_OCInitStruct: refer to the definition of OCInitType
- OCMode
* TIM_OCMODE_TIMING
* TIM_OCMODE_ACTIVE
* TIM_OCMODE_INACTIVE
* TIM_OCMODE_TOGGLE
* TIM_FORCED_ACTION_INACTIVE
* TIM_FORCED_ACTION_ACTIVE
* TIM_OCMODE_PWM1
* TIM_OCMODE_PWM2
* TIM_OCMODE_OPMOD_RETRIG1
* TIM_OCMODE_OPMOD_RETRIG2
* TIM_OCMODE_COMBI_PWM1
* TIM_OCMODE_COMBI_PWM2
- OutputState
* TIM_OUTPUT_STATE_DISABLE
* TIM_OUTPUT_STATE_ENABLE
- OutputNState
* TIM_OUTPUT_NSTATE_DISABLE
* TIM_OUTPUT_NSTATE_ENABLE
- Pulse
* GTIM1 and GTIM4 range from 0x00000000 to 0xffffffff, but the others range from 0x0000 to 0xffff.
- OCPolarity
* TIM_OC_POLARITY_HIGH
* TIM_OC_POLARITY_LOW
- OCNPolarity
* TIM_OCN_POLARITY_HIGH
* TIM_OCN_POLARITY_LOW
- OCIdleState
* TIM_OC_IDLE_STATE_SET
* TIM_OC_IDLE_STATE_RESET
- OCNIdleState
* TIM_OCN_IDLE_STATE_SET
* TIM_OCN_IDLE_STATE_RESET
return none
void TIM_InitOc3(TIM_Module* TIMx, OCInitType* TIM_OCInitStruct)Initializes the TIMx Channel 3.
Source comment
name TIM_InitOc3
fun Initializes the TIMx Channel 3.
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
- ATIM3
- GTIM1
- GTIM2
- GTIM3
- GTIM4
- GTIM5
- GTIM6
- GTIM7
- GTIM8
- GTIM9
- GTIM10
param TIM_OCInitStruct: refer to the definition of OCInitType
- OCMode
* TIM_OCMODE_TIMING
* TIM_OCMODE_ACTIVE
* TIM_OCMODE_INACTIVE
* TIM_OCMODE_TOGGLE
* TIM_FORCED_ACTION_INACTIVE
* TIM_FORCED_ACTION_ACTIVE
* TIM_OCMODE_PWM1
* TIM_OCMODE_PWM2
* TIM_OCMODE_OPMOD_RETRIG1
* TIM_OCMODE_OPMOD_RETRIG2
* TIM_OCMODE_COMBI_PWM1
* TIM_OCMODE_COMBI_PWM2
- OutputState
* TIM_OUTPUT_STATE_DISABLE
* TIM_OUTPUT_STATE_ENABLE
- OutputNState
* TIM_OUTPUT_NSTATE_DISABLE
* TIM_OUTPUT_NSTATE_ENABLE
- Pulse
* GTIM1 and GTIM4 range from 0x00000000 to 0xffffffff, but the others range from 0x0000 to 0xffff.
- OCPolarity
* TIM_OC_POLARITY_HIGH
* TIM_OC_POLARITY_LOW
- OCNPolarity
* TIM_OCN_POLARITY_HIGH
* TIM_OCN_POLARITY_LOW
- OCIdleState
* TIM_OC_IDLE_STATE_SET
* TIM_OC_IDLE_STATE_RESET
- OCNIdleState
* TIM_OCN_IDLE_STATE_SET
* TIM_OCN_IDLE_STATE_RESET
return none
void TIM_InitOc4(TIM_Module* TIMx, OCInitType* TIM_OCInitStruct)Initializes the TIMx Channel 4.
Source comment
name TIM_InitOc4
fun Initializes the TIMx Channel 4.
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
- ATIM3
- GTIM1
- GTIM2
- GTIM3
- GTIM4
- GTIM5
- GTIM6
- GTIM7
- GTIM8
- GTIM9
- GTIM10
param TIM_OCInitStruct: refer to the definition of OCInitType
- OCMode
* TIM_OCMODE_TIMING
* TIM_OCMODE_ACTIVE
* TIM_OCMODE_INACTIVE
* TIM_OCMODE_TOGGLE
* TIM_FORCED_ACTION_INACTIVE
* TIM_FORCED_ACTION_ACTIVE
* TIM_OCMODE_PWM1
* TIM_OCMODE_PWM2
* TIM_OCMODE_OPMOD_RETRIG1
* TIM_OCMODE_OPMOD_RETRIG2
* TIM_OCMODE_COMBI_PWM1
* TIM_OCMODE_COMBI_PWM2
- OutputState
* TIM_OUTPUT_STATE_DISABLE
* TIM_OUTPUT_STATE_ENABLE
- OutputNState
* TIM_OUTPUT_NSTATE_DISABLE
* TIM_OUTPUT_NSTATE_ENABLE
- Pulse
* GTIM1 and GTIM4 range from 0x00000000 to 0xffffffff, but the others range from 0x0000 to 0xffff.
- OCPolarity
* TIM_OC_POLARITY_HIGH
* TIM_OC_POLARITY_LOW
- OCNPolarity
* TIM_OCN_POLARITY_HIGH
* TIM_OCN_POLARITY_LOW
- OCIdleState
* TIM_OC_IDLE_STATE_SET
* TIM_OC_IDLE_STATE_RESET
- OCNIdleState
* TIM_OCN_IDLE_STATE_SET
* TIM_OCN_IDLE_STATE_RESET
return none
void TIM_InitOc5(TIM_Module* TIMx, OCInitType* TIM_OCInitStruct)Initializes the TIMx Channel 5.
Source comment
name TIM_InitOc5
fun Initializes the TIMx Channel 5.
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
- ATIM3
- GTIM8
- GTIM9
- GTIM10
param TIM_OCInitStruct: refer to the definition of OCInitType
- OCMode
* TIM_OCMODE_TIMING
* TIM_OCMODE_ACTIVE
* TIM_OCMODE_INACTIVE
* TIM_OCMODE_TOGGLE
* TIM_FORCED_ACTION_INACTIVE
* TIM_FORCED_ACTION_ACTIVE
* TIM_OCMODE_PWM1
* TIM_OCMODE_PWM2
- OutputState
* TIM_OUTPUT_STATE_DISABLE
* TIM_OUTPUT_STATE_ENABLE
- Pulse
* 0x0000 ~ 0xFFFF
- OCPolarity
* TIM_OC_POLARITY_HIGH
* TIM_OC_POLARITY_LOW
- OCIdleState
* TIM_OC_IDLE_STATE_SET
* TIM_OC_IDLE_STATE_RESET
return none
void TIM_InitOc6(TIM_Module* TIMx, OCInitType* TIM_OCInitStruct)Initializes the TIMx Channel 6.
Source comment
name TIM_InitOc6
fun Initializes the TIMx Channel 6.
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
- ATIM3
param TIM_OCInitStruct: refer to the definition of OCInitType
- OCMode
* TIM_OCMODE_TIMING
* TIM_OCMODE_ACTIVE
* TIM_OCMODE_INACTIVE
* TIM_OCMODE_TOGGLE
* TIM_FORCED_ACTION_INACTIVE
* TIM_FORCED_ACTION_ACTIVE
* TIM_OCMODE_PWM1
* TIM_OCMODE_PWM2
- OutputState
* TIM_OUTPUT_STATE_DISABLE
* TIM_OUTPUT_STATE_ENABLE
- Pulse
* 0x0000 ~ 0xFFFF
- OCPolarity
* TIM_OC_POLARITY_HIGH
* TIM_OC_POLARITY_LOW
- OCIdleState
* TIM_OC_IDLE_STATE_SET
* TIM_OC_IDLE_STATE_RESET
return none
void TIM_ICInit(TIM_Module* TIMx, TIM_ICInitType* TIM_ICInitStruct)Initializes the TIM peripheral according to the specified parameters in the TIM_ICInitStruct.
Source comment
name TIM_ICInit
fun Initializes the TIM peripheral according to the specified
parameters in the TIM_ICInitStruct.
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
- ATIM3
- GTIM1
- GTIM2
- GTIM3
- GTIM4
- GTIM5
- GTIM6
- GTIM7
- GTIM8
- GTIM9
- GTIM10
param TIM_ICInitStruct: refer to the definition of TIM_ICInitType
- Channel
* TIM_CH_1
* TIM_CH_2
* TIM_CH_3
* TIM_CH_4
- ICPolarity
* TIM_IC_POLARITY_RISING
* TIM_IC_POLARITY_FALLING
- ICSelection
* TIM_IC_SELECTION_DIRECTTI
* TIM_IC_SELECTION_INDIRECTTI
* TIM_IC_SELECTION_TRC
- ICPrescaler
* TIM_IC_PSC_DIV1
* TIM_IC_PSC_DIV2
* TIM_IC_PSC_DIV4
* TIM_IC_PSC_DIV8
- ICFilter
* ICFilter can be a number between 0x0 and 0xF
return none
void TIM_ConfigPwmIc(TIM_Module* TIMx, TIM_ICInitType* TIM_ICInitStruct)Configures the TIM peripheral according to the specified parameters in the TIM_ICInitStruct to measure an external PWM signal.
Source comment
name TIM_ConfigPwmIc
fun Configures the TIM peripheral according to the specified
parameters in the TIM_ICInitStruct to measure an external PWM signal.
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
- ATIM3
- GTIM1
- GTIM2
- GTIM3
- GTIM4
- GTIM5
- GTIM6
- GTIM7
- GTIM8
- GTIM9
- GTIM10
param TIM_ICInitStruct: refer to the definition of TIM_ICInitType
- Channel
* TIM_CH_1
* TIM_CH_2
- ICPolarity
* TIM_IC_POLARITY_RISING
* TIM_IC_POLARITY_FALLING
- ICSelection
* TIM_IC_SELECTION_DIRECTTI
* TIM_IC_SELECTION_INDIRECTTI
- ICPrescaler
* TIM_IC_PSC_DIV1
* TIM_IC_PSC_DIV2
* TIM_IC_PSC_DIV4
* TIM_IC_PSC_DIV8
- ICFilter
* ICFilter can be a number between 0x0 and 0xF
return none
void TIM_ConfigBkdt(TIM_Module* TIMx, TIM_BDTRInitType* TIM_BDTRInitStruct)Configures the: Break feature, dead time, Lock level, the OSSI, the OSSR State and the AOE(automatic output enable).
Source comment
name TIM_ConfigBkdt
fun Configures the: Break feature, dead time, Lock level, the OSSI,
the OSSR State and the AOE(automatic output enable).
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
- ATIM3
- GTIM8
- GTIM9
- GTIM10
param TIM_BDTRInitStruct: refer to the definition of TIM_BDTRInitType
- OSSRState
* TIM_OSSR_STATE_ENABLE
* TIM_OSSR_STATE_DISABLE
- OSSIState
* TIM_OSSI_STATE_ENABLE
* TIM_OSSI_STATE_DISABLE
- LOCKLevel
* TIM_LOCK_LEVEL_OFF
* TIM_LOCK_LEVEL_1
* TIM_LOCK_LEVEL_2
* TIM_LOCK_LEVEL_3
- DeadTime
* DeadTime can be a number between 0x00 and 0xFF
- Break
* TIM_BREAK_IN_ENABLE
* TIM_BREAK_IN_DISABLE
- BreakPolarity
* TIM_BREAK_POLARITY_LOW
* TIM_BREAK_POLARITY_HIGH
- Bidirection
* TIM_BREAK_BID_ENABLE
* TIM_BREAK_BID_DISABLE
- AutomaticOutput
* TIM_AUTO_OUTPUT_ENABLE
* TIM_AUTO_OUTPUT_DISABLE
- Break2
* TIM_BREAK2_IN_ENABLE
* TIM_BREAK2_IN_DISABLE
- Break2Polarity
* TIM_BREAK2_POLARITY_LOW
* TIM_BREAK2_POLARITY_HIGH
- Bidirection2
* TIM_BREAK2_BID_ENABLE
* TIM_BREAK2_BID_DISABLE
return none
void TIM_BreakFiltConfig(TIM_Module* TIMx, TIM_FiltInitType* TIM_FiltInitStruct)Config the filter of break input.
Source comment
name TIM_BreakFiltConfig
fun Config the filter of break input.
param TIMx:
- ATIM1
- ATIM2
- ATIM3
- GTIM8
- GTIM9
- GTIM10
param TIM_FiltInitStruct:
- refer to the definition of TIM_FiltInitType
return none
void TIM_BreakFiltEnable(TIM_Module* TIMx,FunctionalState Cmd)Enable or disable the filter of break input.
Source comment
name TIM_BreakFiltEnable
fun Enable or disable the filter of break input.
param TIMx:
- ATIM1
- ATIM2
- ATIM3
- GTIM8
- GTIM9
- GTIM10
param Cmd :
- ENABLE
- DISABLE
return none
void TIM_Break2FiltEnable(TIM_Module* TIMx,FunctionalState Cmd)Enable or disable the filter of break2 input.
Source comment
name TIM_Break2FiltEnable
fun Enable or disable the filter of break2 input.
param TIMx:
- ATIM1
- ATIM2
- ATIM3
param Cmd :
- ENABLE
- DISABLE
return none
void TIM_Break2FiltConfig(TIM_Module* TIMx, TIM_FiltInitType* TIM_FiltInitStruct)Config the filter of break2 input.
Source comment
name TIM_Break2FiltConfig
fun Config the filter of break2 input.
param TIMx:
- ATIM1
- ATIM2
- ATIM3
param TIM_FiltInitStruct:
- refer to the definition of TIM_FiltInitType
return none
void TIM_BreakInputSourceEnable(TIM_Module* TIMx, uint32_t Source, uint32_t Polarity, FunctionalState Cmd)Enable or disable the break input source , and set the polarity of the break input source.
Source comment
name TIM_BreakInputSourceEnable
fun Enable or disable the break input source , and set the polarity of the break input source.
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
- ATIM3
- GTIM8
- GTIM9
- GTIM10
param Source
- TIM_BREAK_LOCKUP
- TIM_BREAK_PVD
- TIM_BREAK_SMPAR
- TIM_BREAK_FLECC
- TIM_BREAK_SMECC
- TIM_BREAK_IOM
- TIM_BREAK_DSMU0
- TIM_BREAK_DSMU1
- TIM_BREAK_DSMU2
- TIM_BREAK_DSMU3
param Polarity
- TIM_BREAK_SOURCE_POLARITY_INVERT
- TIM_BREAK_SOURCE_POLARITY_NONINVERT
param Cmd
- ENABLE
- DISABLE
return none
void TIM_Break2InputSourceEnable(TIM_Module* TIMx, uint32_t Source, uint32_t Polarity, FunctionalState Cmd)Enable or disable the break2 input source , and set the polarity of the break2 input source.
Source comment
name TIM_Break2InputSourceEnable
fun Enable or disable the break2 input source , and set the polarity of the break2 input source.
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
- ATIM3
param Source
- TIM_BREAK2_IOM
- TIM_BREAK2_DSMU0
- TIM_BREAK2_DSMU1
- TIM_BREAK2_DSMU2
- TIM_BREAK2_DSMU3
param Polarity
- TIM_BREAK2_SOURCE_POLARITY_INVERT
- TIM_BREAK2_SOURCE_POLARITY_NONINVERT
param Cmd
- ENABLE
- DISABLE
return none
void TIM_BidirectionDisarm(TIM_Module* TIMx)Disarm bidirection of break.
Source comment
name TIM_BidirectionDisarm
fun Disarm bidirection of break.
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
- ATIM3
- GTIM8
- GTIM9
- GTIM10
return none
void TIM_BidirectionRearm(TIM_Module* TIMx)Rearm bidirection of break.
Source comment
name TIM_BidirectionRearm
fun Rearm bidirection of break.
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
- ATIM3
- GTIM8
- GTIM9
- GTIM10
return none
void TIM_Bidirection2Disarm(TIM_Module* TIMx)Disarm bidirection of break2.
Source comment
name TIM_Bidirection2Disarm
fun Disarm bidirection of break2.
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
- ATIM3
return none
void TIM_Bidirection2Rearm(TIM_Module* TIMx)Rearm bidirection of break2.
Source comment
name TIM_Bidirection2Rearm
fun Rearm bidirection of break2.
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
- ATIM3
return none
void TIM_InitTimBaseStruct(TIM_TimeBaseInitType* TIM_TimeBaseInitStruct)Fills each TIM_TimeBaseInitStruct member with its default value.
Source comment
name TIM_InitTimBaseStruct
fun Fills each TIM_TimeBaseInitStruct member with its default value.
param TIM_TimeBaseInitStruct: refer to the definition of TIM_TimeBaseInitType
- Prescaler
* 0x0000 ~ 0xFFFF
- CounterMode
* TIM_CNT_MODE_UP
* TIM_CNT_MODE_DOWN
* TIM_CNT_MODE_CENTER_ALIGN1
* TIM_CNT_MODE_CENTER_ALIGN2
* TIM_CNT_MODE_CENTER_ALIGN3
- Period
* GTIM1 and GTIM4 range from 0x00000000 to 0xffffffff, but the others range from 0x0000 to 0xffff.
- ClkDiv
* TIM_CLK_DIV1
* TIM_CLK_DIV2
* TIM_CLK_DIV4
- RepetCnt
* 0x00 ~ 0xFF
- CapCh1Sel
* TIM_CAPCH1SEL_0
* TIM_CAPCH1SEL_5
* TIM_CAPCH1SEL_6
* TIM_CAPCH1SEL_7
- CapCh2Sel
* TIM_CAPCH2SEL_0
* TIM_CAPCH2SEL_1
* TIM_CAPCH2SEL_4
* TIM_CAPCH2SEL_TIMXCAPLSE
- CapCh3Sel
* TIM_CAPCH3SEL_0
* TIM_CAPCH3SEL_1
* TIM_CAPCH3SEL_TIMXCAPLSI
- CapCh4Sel
* TIM_CAPCH4SEL_0
* TIM_CAPCH4SEL_1
* TIM_CAPCH4SEL_2
* TIM_CAPCH4SEL_TIMXCAPHSEDIV128
- EtrOrClr
* TIM_ETRSEL
* TIM_CLRSEL
- CapEtrClrSel
* TIM_CAPETRSEL_0
* TIM_CAPETRSEL_8
* TIM_CAPETRSEL_10
* TIM_CAPETRSEL_11
* TIM_CAPETRSEL_12
* TIM_CAPETRSEL_13
return none
void TIM_InitOcStruct(OCInitType* TIM_OCInitStruct)Fills each TIM_OCInitStruct member with its default value.
Source comment
name TIM_InitOcStruct
fun Fills each TIM_OCInitStruct member with its default value.
param TIM_OCInitStruct: refer to the definition of OCInitType
- OCMode
* TIM_OCMODE_TIMING
* TIM_OCMODE_ACTIVE
* TIM_OCMODE_INACTIVE
* TIM_OCMODE_TOGGLE
* TIM_FORCED_ACTION_INACTIVE
* TIM_FORCED_ACTION_ACTIVE
* TIM_OCMODE_PWM1
* TIM_OCMODE_PWM2
* TIM_OCMODE_OPMOD_RETRIG1
* TIM_OCMODE_OPMOD_RETRIG2
* TIM_OCMODE_COMBI_PWM1
* TIM_OCMODE_COMBI_PWM2
- OutputState
* TIM_OUTPUT_STATE_DISABLE
* TIM_OUTPUT_STATE_ENABLE
- OutputNState
* TIM_OUTPUT_NSTATE_DISABLE
* TIM_OUTPUT_NSTATE_ENABLE
- Pulse
* 0x0000 ~ 0xFFFF
- OCPolarity
* TIM_OC_POLARITY_HIGH
* TIM_OC_POLARITY_LOW
- OCNPolarity
* TIM_OCN_POLARITY_HIGH
* TIM_OCN_POLARITY_LOW
- OCIdleState
* TIM_OC_IDLE_STATE_SET
* TIM_OC_IDLE_STATE_RESET
- OCNIdleState
* TIM_OCN_IDLE_STATE_SET
* TIM_OCN_IDLE_STATE_RESET
return none
void TIM_InitIcStruct(TIM_ICInitType* TIM_ICInitStruct)Fills each TIM_ICInitStruct member with its default value.
Source comment
name TIM_InitIcStruct
fun Fills each TIM_ICInitStruct member with its default value.
param TIM_ICInitStruct: refer to the definition of TIM_ICInitType
- Channel
* TIM_CH_1
* TIM_CH_2
* TIM_CH_3
* TIM_CH_4
- ICPolarity
* TIM_IC_POLARITY_RISING
* TIM_IC_POLARITY_FALLING
- ICSelection
* TIM_IC_SELECTION_DIRECTTI
* TIM_IC_SELECTION_INDIRECTTI
* TIM_IC_SELECTION_TRC
- ICPrescaler
* TIM_IC_PSC_DIV1
* TIM_IC_PSC_DIV2
* TIM_IC_PSC_DIV4
* TIM_IC_PSC_DIV8
- ICFilter
* ICFilter can be a number between 0x0 and 0xF
return none
void TIM_InitBkdtStruct(TIM_BDTRInitType* TIM_BDTRInitStruct)Fills each TIM_BDTRInitStruct member with its default value.
Source comment
name TIM_InitBkdtStruct
fun Fills each TIM_BDTRInitStruct member with its default value.
param TIM_BDTRInitStruct: refer to the definition of TIM_BDTRInitType
- OSSRState
* TIM_OSSR_STATE_ENABLE
* TIM_OSSR_STATE_DISABLE
- OSSIState
* TIM_OSSI_STATE_ENABLE
* TIM_OSSI_STATE_DISABLE
- LOCKLevel
* TIM_LOCK_LEVEL_OFF
* TIM_LOCK_LEVEL_1
* TIM_LOCK_LEVEL_2
* TIM_LOCK_LEVEL_3
- DeadTime
* DeadTime can be a number between 0x00 and 0xFF
- Break
* TIM_BREAK_IN_ENABLE
* TIM_BREAK_BID_DISABLE
- BreakPolarity
* TIM_BREAK_POLARITY_LOW
* TIM_BREAK_POLARITY_HIGH
- Bidirection
* TIM_BREAK_BID_ENABLE
* TIM_BREAK_BID_DISABLE
- AutomaticOutput
* TIM_AUTO_OUTPUT_ENABLE
* TIM_AUTO_OUTPUT_DISABLE
- Break2
* TIM_BREAK2_IN_ENABLE
* TIM_BREAK2_IN_DISABLE
- Break2Polarity
* TIM_BREAK2_POLARITY_LOW
* TIM_BREAK2_POLARITY_HIGH
- Bidirection2
* TIM_BREAK2_BID_ENABLE
* TIM_BREAK2_BID_DISABLE
return none
void TIM_Enable(TIM_Module* TIMx, FunctionalState Cmd)Enables or disables the specified TIM peripheral.
Source comment
name TIM_Enable
fun Enables or disables the specified TIM peripheral.
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
- ATIM3
- GTIM1
- GTIM2
- GTIM3
- GTIM4
- GTIM5
- GTIM6
- GTIM7
- GTIM8
- GTIM9
- GTIM10
- BTIM1
- BTIM2
param Cmd :
- ENABLE
- DISABLE
return none
void TIM_EnableCtrlPwmOutputs(TIM_Module* TIMx, FunctionalState Cmd)Enables or disables the TIM peripheral Main Outputs.
Source comment
name TIM_EnableCtrlPwmOutputs
fun Enables or disables the TIM peripheral Main Outputs.
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
- ATIM3
- GTIM8
- GTIM9
- GTIM10
param Cmd :
- ENABLE
- DISABLE
return none
void TIM_ConfigInt(TIM_Module* TIMx, uint32_t TIM_IT, FunctionalState Cmd)Enables or disables the specified TIM interrupts.
Source comment
name TIM_ConfigInt
fun Enables or disables the specified TIM interrupts.
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
- ATIM3
- GTIM1
- GTIM2
- GTIM3
- GTIM4
- GTIM5
- GTIM6
- GTIM7
- GTIM8
- GTIM9
- GTIM10
- BTIM1
- BTIM2
param TIM_IT:
- TIM_INT_CC1
- TIM_INT_CC2
- TIM_INT_CC3
- TIM_INT_CC4
- TIM_INT_CC5
- TIM_INT_CC6
- TIM_INT_CC7
- TIM_INT_CC8
- TIM_INT_CC9
- TIM_INT_UPDATE
- TIM_INT_TRIG
- TIM_INT_BREAK
- TIM_INT_COM
param Cmd :
- ENABLE
- DISABLE
return none
void TIM_GenerateEvent(TIM_Module* TIMx, uint32_t TIM_EventSource)Configures the TIMx event to be generate by software.
Source comment
name TIM_GenerateEvent
fun Configures the TIMx event to be generate by software.
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
- ATIM3
- GTIM1
- GTIM2
- GTIM3
- GTIM4
- GTIM5
- GTIM6
- GTIM7
- GTIM8
- GTIM9
- GTIM10
- BTIM1
- BTIM2
param TIM_EventSource:
- TIM_EVT_SRC_CC1
- TIM_EVT_SRC_CC2
- TIM_EVT_SRC_CC3
- TIM_EVT_SRC_CC4
- TIM_EVT_SRC_UPDATE
- TIM_EVT_SRC_COM
- TIM_EVT_SRC_TRIG
- TIM_EVT_SRC_BREAK
- TIM_EVT_SRC_BREAK2
return none
void TIM_ConfigDma(TIM_Module* TIMx, uint32_t TIM_DMABase, uint32_t TIM_DMABurstLength)Configures the TIMx’s DMA interface.
Source comment
name TIM_ConfigDma
fun Configures the TIMx's DMA interface.
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
- ATIM3
- GTIM1
- GTIM2
- GTIM3
- GTIM4
- GTIM5
- GTIM6
- GTIM7
- GTIM8
- GTIM9
- GTIM10
param TIM_DMABase:
- TIM_DMABASE_CTRL1
- TIM_DMABASE_CTRL2
- TIM_DMABASE_STS
- TIM_DMABASE_EVTGEN
- TIM_DMABASE_SMCTRL
- TIM_DMABASE_DMAINTEN
- TIM_DMABASE_CAPCMPMOD1
- TIM_DMABASE_CAPCMPMOD2
- TIM_DMABASE_CAPCMPMOD3
- TIM_DMABASE_CAPCMPEN
- TIM_DMABASE_CAPCMPDAT1
- TIM_DMABASE_CAPCMPDAT2
- TIM_DMABASE_CAPCMPDAT3
- TIM_DMABASE_CAPCMPDAT4
- TIM_DMABASE_CAPCMPDAT5
- TIM_DMABASE_CAPCMPDAT6
- TIM_DMABASE_PSC
- TIM_DMABASE_AR
- TIM_DMABASE_CNT
- TIM_DMABASE_REPCNT
- TIM_DMABASE_BKDT
- TIM_DMABASE_CAPCMPDAT7
- TIM_DMABASE_CAPCMPDAT8
- TIM_DMABASE_CAPCMPDAT9
- TIM_DMABASE_BKFR
- TIM_DMABASE_C1FILT
- TIM_DMABASE_C2FILT
- TIM_DMABASE_C3FILT
- TIM_DMABASE_C4FILT
- TIM_DMABASE_FILTO
- TIM_DMABASE_INSEL
- TIM_DMABASE_AF1
- TIM_DMABASE_AF2
- TIM_DMABASE_BKFR2
- TIM_DMABASE_SLIDFPSC
param TIM_DMABurstLength:
- This parameter can be one value between:
TIM_DMABURST_LENGTH_1TRANSFER and TIM_DMABURST_LENGTH_35TRANSFERS.
return none
void TIM_EnableDma(TIM_Module* TIMx, uint32_t TIM_DMASource, FunctionalState Cmd)Enables or disables the TIMx’s DMA Requests.
Source comment
name TIM_EnableDma
fun Enables or disables the TIMx's DMA Requests.
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
- ATIM3
- GTIM1
- GTIM2
- GTIM3
- GTIM4
- GTIM5
- GTIM6
- GTIM7
- GTIM8
- GTIM9
- GTIM10
param TIM_DMASource:
- TIM_DMA_CC1
- TIM_DMA_CC2
- TIM_DMA_CC3
- TIM_DMA_CC4
- TIM_DMA_UPDATE
- TIM_DMA_COM
- TIM_DMA_TRIG
param Cmd:
- DISABLE
- ENABLE
return none
void TIM_ConfigInternalClk(TIM_Module* TIMx)Configures the TIMx internal Clock
Source comment
name TIM_ConfigInternalClk
fun Configures the TIMx internal Clock
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
- ATIM3
- GTIM1
- GTIM2
- GTIM3
- GTIM4
- GTIM5
- GTIM6
- GTIM7
- GTIM8
- GTIM9
- GTIM10
return none
void TIM_ConfigInternalTrigToExt(TIM_Module* TIMx, uint32_t TIM_InputTriggerSource)Configures the TIMx Internal Trigger as External Clock
Source comment
name TIM_ConfigInternalTrigToExt
fun Configures the TIMx Internal Trigger as External Clock
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
- ATIM3
- GTIM1
- GTIM2
- GTIM3
- GTIM4
- GTIM5
- GTIM6
- GTIM7
- GTIM8
- GTIM9
- GTIM10
param TIM_InputTriggerSource:
- TIM_TRIG_SEL_IN_TR0
- TIM_TRIG_SEL_IN_TR1
- TIM_TRIG_SEL_IN_TR2
- TIM_TRIG_SEL_IN_TR3
- TIM_TRIG_SEL_IN_TR4
- TIM_TRIG_SEL_IN_TR5
- TIM_TRIG_SEL_IN_TR6
- TIM_TRIG_SEL_IN_TR7
- TIM_TRIG_SEL_IN_TR8
- TIM_TRIG_SEL_IN_TR9
- TIM_TRIG_SEL_IN_TR10
- TIM_TRIG_SEL_IN_TR11
- TIM_TRIG_SEL_IN_TR12
- TIM_TRIG_SEL_IN_TR13
- TIM_TRIG_SEL_IN_TR14
return none
void TIM_ConfigExtTrigAsClk(TIM_Module* TIMx, uint32_t TIM_TIxExternalCLKSource, uint32_t IcPolarity, uint32_t ICFilter)Configures the TIMx Trigger as External Clock
Source comment
name TIM_ConfigExtTrigAsClk
fun Configures the TIMx Trigger as External Clock
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
- ATIM3
- GTIM1
- GTIM2
- GTIM3
- GTIM4
- GTIM5
- GTIM6
- GTIM7
- GTIM8
- GTIM9
- GTIM10
param TIM_TIxExternalCLKSource:
- TIM_TRIG_SEL_TI1F_ED
- TIM_TRIG_SEL_TI1FP1
- TIM_TRIG_SEL_TI2FP2
param ICPolarity
- TIM_IC_POLARITY_RISING
- TIM_IC_POLARITY_FALLING
param ICFilter
- ICFilter can be a number between 0x0 and 0xF
return none
void TIM_ConfigExtClkMode1(TIM_Module* TIMx,uint32_t TIM_ETRInputSource,uint32_t TIM_ExtTRGPrescaler,uint32_t TIM_ExtTRGPolarity,uint32_t ExtTRGFilter)Configures the External clock Mode1
Source comment
name TIM_ConfigExtClkMode1
fun Configures the External clock Mode1
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
- ATIM3
- GTIM1
- GTIM2
- GTIM3
- GTIM4
- GTIM5
- GTIM6
- GTIM7
- GTIM8
- GTIM9
- GTIM10
param TIM_ETRInputSource:
- TIM_CAPETRSEL_0
- TIM_CAPETRSEL_8
- TIM_CAPETRSEL_9
- TIM_CAPETRSEL_10
- TIM_CAPETRSEL_11
- TIM_CAPETRSEL_12
- TIM_CAPETRSEL_13
param TIM_ExtTRGPrescaler:
- TIM_EXT_TRG_PSC_OFF
- TIM_EXT_TRG_PSC_DIV2
- TIM_EXT_TRG_PSC_DIV4
- TIM_EXT_TRG_PSC_DIV8
param TIM_ExtTRGPolarity
- TIM_EXT_TRIG_POLARITY_INVERTED
- TIM_EXT_TRIG_POLARITY_NONINVERTED
param ExtTRGFilter
- ExtTRGFilter can be a number between 0x0 and 0xF
return none
void TIM_ConfigExtClkMode2(TIM_Module* TIMx,uint32_t TIM_ETRInputSource,uint32_t TIM_ExtTRGPrescaler,uint32_t TIM_ExtTRGPolarity,uint32_t ExtTRGFilter)Configures the External clock Mode2
Source comment
name TIM_ConfigExtClkMode2
fun Configures the External clock Mode2
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
- ATIM3
- GTIM1
- GTIM2
- GTIM3
- GTIM4
- GTIM5
- GTIM6
- GTIM7
- GTIM8
- GTIM9
- GTIM10
param TIM_ETRInputSource:
- TIM_CAPETRSEL_0
- TIM_CAPETRSEL_8
- TIM_CAPETRSEL_9
- TIM_CAPETRSEL_10
- TIM_CAPETRSEL_11
- TIM_CAPETRSEL_12
- TIM_CAPETRSEL_13
param TIM_ExtTRGPrescaler:
- TIM_EXT_TRG_PSC_OFF
- TIM_EXT_TRG_PSC_DIV2
- TIM_EXT_TRG_PSC_DIV4
- TIM_EXT_TRG_PSC_DIV8
param TIM_ExtTRGPolarity
- TIM_EXT_TRIG_POLARITY_INVERTED
- TIM_EXT_TRIG_POLARITY_NONINVERTED
param ExtTRGFilter
- ExtTRGFilter can be a number between 0x0 and 0xF
return none
void TIM_ConfigPrescaler(TIM_Module* TIMx, uint32_t Prescaler, uint32_t TIM_PSCReloadMode)Configures the TIMx Prescaler.
Source comment
name TIM_ConfigPrescaler
fun Configures the TIMx Prescaler.
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
- ATIM3
- GTIM1
- GTIM2
- GTIM3
- GTIM4
- GTIM5
- GTIM6
- GTIM7
- GTIM8
- GTIM9
- GTIM10
- BTIM1
- BTIM2
param Prescaler:
- 0x0000 ~ 0xFFFF
param TIM_PSCReloadMode
- TIM_PSC_RELOAD_MODE_UPDATE
- TIM_PSC_RELOAD_MODE_IMMEDIATE
return none
void TIM_ConfigCntMode(TIM_Module* TIMx, uint32_t CntMode)Specifies the TIMx Counter Mode to be used.
Source comment
name TIM_ConfigCntMode
fun Specifies the TIMx Counter Mode to be used.
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
- ATIM3
- GTIM1
- GTIM2
- GTIM3
- GTIM4
- GTIM5
- GTIM6
- GTIM7
- GTIM8
- GTIM9
- GTIM10
- BTIM1
- BTIM2
param CntMode
- TIM_CNT_MODE_UP
- TIM_CNT_MODE_DOWN
- TIM_CNT_MODE_CENTER_ALIGN1
- TIM_CNT_MODE_CENTER_ALIGN2
- TIM_CNT_MODE_CENTER_ALIGN3
return none
void TIM_ConfigEncoderInterface(TIM_Module* TIMx,uint32_t TIM_EncoderMode,uint32_t TIM_IC1Polarity,uint32_t TIM_IC2Polarity)Configures the TIMx Encoder Interface.
Source comment
name TIM_ConfigEncoderInterface
fun Configures the TIMx Encoder Interface.
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
- ATIM3
- GTIM1
- GTIM2
- GTIM3
- GTIM4
- GTIM5
- GTIM6
- GTIM7
- GTIM8
- GTIM9
- GTIM10
param TIM_EncoderMode
- TIM_ENCODE_QUA_MODE_TI1
- TIM_ENCODE_QUA_MODE_TI2
- TIM_ENCODE_QUA_MODE_TI12
- TIM_ENCODE_QUA_MODE_SINGLE_TI1
- TIM_ENCODE_QUA_MODE_SINGLE_TI2
- TIM_ENCODE_DUL_CLKPLUS_MODE1
- TIM_ENCODE_DUL_CLKPLUS_MODE2
- TIM_ENCODE_SINGLE_CLKPLUS_MODE1
- TIM_ENCODE_SINGLE_CLKPLUS_MODE2
param TIM_IC1Polarity
- TIM_IC_POLARITY_FALLING
- TIM_IC_POLARITY_RISING
param TIM_IC2Polarity
- TIM_IC_POLARITY_FALLING
- TIM_IC_POLARITY_RISING
return none
void TIM_ConfigForcedOc1(TIM_Module* TIMx, uint32_t TIM_ForcedAction)Forces the TIMx output 1 waveform to active or inactive level.
Source comment
name TIM_ConfigForcedOc1
fun Forces the TIMx output 1 waveform to active or inactive level.
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
- ATIM3
- GTIM1
- GTIM2
- GTIM3
- GTIM4
- GTIM5
- GTIM6
- GTIM7
- GTIM8
- GTIM9
- GTIM10
param TIM_ForcedAction
- TIM_FORCED_ACTION_ACTIVE
- TIM_FORCED_ACTION_INACTIVE
return none
void TIM_ConfigForcedOc2(TIM_Module* TIMx, uint32_t TIM_ForcedAction)Forces the TIMx output 2 waveform to active or inactive level.
Source comment
name TIM_ConfigForcedOc2
fun Forces the TIMx output 2 waveform to active or inactive level.
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
- ATIM3
- GTIM1
- GTIM2
- GTIM3
- GTIM4
- GTIM5
- GTIM6
- GTIM7
- GTIM8
- GTIM9
- GTIM10
param TIM_ForcedAction
- TIM_FORCED_ACTION_ACTIVE
- TIM_FORCED_ACTION_INACTIVE
return none
void TIM_ConfigForcedOc3(TIM_Module* TIMx, uint32_t TIM_ForcedAction)Forces the TIMx output 3 waveform to active or inactive level.
Source comment
name TIM_ConfigForcedOc3
fun Forces the TIMx output 3 waveform to active or inactive level.
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
- ATIM3
- GTIM1
- GTIM2
- GTIM3
- GTIM4
- GTIM5
- GTIM6
- GTIM7
- GTIM8
- GTIM9
- GTIM10
param TIM_ForcedAction
- TIM_FORCED_ACTION_ACTIVE
- TIM_FORCED_ACTION_INACTIVE
return none
void TIM_ConfigForcedOc4(TIM_Module* TIMx, uint32_t TIM_ForcedAction)Forces the TIMx output 4 waveform to active or inactive level.
Source comment
name TIM_ConfigForcedOc4
fun Forces the TIMx output 4 waveform to active or inactive level.
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
- ATIM3
- GTIM1
- GTIM2
- GTIM3
- GTIM4
- GTIM5
- GTIM6
- GTIM7
- GTIM8
- GTIM9
- GTIM10
param TIM_ForcedAction
- TIM_FORCED_ACTION_ACTIVE
- TIM_FORCED_ACTION_INACTIVE
return none
void TIM_ConfigForcedOc5(TIM_Module* TIMx, uint32_t TIM_ForcedAction)Forces the TIMx output 5 waveform to active or inactive level.
Source comment
name TIM_ConfigForcedOc5
fun Forces the TIMx output 5 waveform to active or inactive level.
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
- ATIM3
- GTIM8
- GTIM9
- GTIM10
param TIM_ForcedAction
- TIM_FORCED_ACTION_ACTIVE
- TIM_FORCED_ACTION_INACTIVE
return none
void TIM_ConfigForcedOc6(TIM_Module* TIMx, uint32_t TIM_ForcedAction)Forces the TIMx output 6 waveform to active or inactive level.
Source comment
name TIM_ConfigForcedOc6
fun Forces the TIMx output 6 waveform to active or inactive level.
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
- ATIM3
param TIM_ForcedAction
- TIM_FORCED_ACTION_ACTIVE
- TIM_FORCED_ACTION_INACTIVE
return none
void TIM_ConfigArPreload(TIM_Module* TIMx, FunctionalState Cmd)Enables or disables TIMx peripheral Preload register on AR.
Source comment
name TIM_ConfigArPreload
fun Enables or disables TIMx peripheral Preload register on AR.
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
- ATIM3
- GTIM1
- GTIM2
- GTIM3
- GTIM4
- GTIM5
- GTIM6
- GTIM7
- GTIM8
- GTIM9
- GTIM10
- BTIM1
- BTIM2
param Cmd
- ENABLE
- DISABLE
return none
void TIM_SelectComEvt(TIM_Module* TIMx, FunctionalState Cmd)Selects the TIM peripheral Commutation event.
Source comment
name TIM_SelectComEvt
fun Selects the TIM peripheral Commutation event.
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
- ATIM3
- GTIM8
- GTIM9
- GTIM10
param Cmd
- ENABLE
- DISABLE
return none
void TIM_SelectCapCmpDmaSrc(TIM_Module* TIMx, FunctionalState Cmd)Selects the TIMx peripheral Capture Compare DMA source.
Source comment
name TIM_SelectCapCmpDmaSrc
fun Selects the TIMx peripheral Capture Compare DMA source.
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
- ATIM3
- GTIM1
- GTIM2
- GTIM3
- GTIM4
- GTIM5
- GTIM6
- GTIM7
- GTIM8
- GTIM9
- GTIM10
param Cmd
- ENABLE
- DISABLE
return none
void TIM_EnableCapCmpPreloadControl(TIM_Module* TIMx, FunctionalState Cmd)Sets or Resets the TIM peripheral Capture Compare Preload Control bit.
Source comment
name TIM_EnableCapCmpPreloadControl
fun Sets or Resets the TIM peripheral Capture Compare Preload Control bit.
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
- ATIM3
- GTIM8
- GTIM9
- GTIM10
param Cmd
- ENABLE
- DISABLE
return none
void TIM_ConfigOc1Preload(TIM_Module* TIMx, uint32_t TIM_OCPreload)Enables or disables the TIMx peripheral Preload register on CCDAT1.
Source comment
name TIM_ConfigOc1Preload
fun Enables or disables the TIMx peripheral Preload register on CCDAT1.
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
- ATIM3
- GTIM1
- GTIM2
- GTIM3
- GTIM4
- GTIM5
- GTIM6
- GTIM7
- GTIM8
- GTIM9
- GTIM10
param TIM_OCPreload
- TIM_OC_PRE_LOAD_ENABLE
- TIM_OC_PRE_LOAD_DISABLE
return none
void TIM_ConfigOc2Preload(TIM_Module* TIMx, uint32_t TIM_OCPreload)Enables or disables the TIMx peripheral Preload register on CCDAT2.
Source comment
name TIM_ConfigOc2Preload
fun Enables or disables the TIMx peripheral Preload register on CCDAT2.
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
- ATIM3
- GTIM1
- GTIM2
- GTIM3
- GTIM4
- GTIM5
- GTIM6
- GTIM7
- GTIM8
- GTIM9
- GTIM10
param TIM_OCPreload
- TIM_OC_PRE_LOAD_ENABLE
- TIM_OC_PRE_LOAD_DISABLE
return none
void TIM_ConfigOc3Preload(TIM_Module* TIMx, uint32_t TIM_OCPreload)Enables or disables the TIMx peripheral Preload register on CCDAT3.
Source comment
name TIM_ConfigOc3Preload
fun Enables or disables the TIMx peripheral Preload register on CCDAT3.
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
- ATIM3
- GTIM1
- GTIM2
- GTIM3
- GTIM4
- GTIM5
- GTIM6
- GTIM7
- GTIM8
- GTIM9
- GTIM10
param TIM_OCPreload
- TIM_OC_PRE_LOAD_ENABLE
- TIM_OC_PRE_LOAD_DISABLE
return none
void TIM_ConfigOc4Preload(TIM_Module* TIMx, uint32_t TIM_OCPreload)Enables or disables the TIMx peripheral Preload register on CCDAT4.
Source comment
name TIM_ConfigOc4Preload
fun Enables or disables the TIMx peripheral Preload register on CCDAT4.
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
- ATIM3
- GTIM1
- GTIM2
- GTIM3
- GTIM4
- GTIM5
- GTIM6
- GTIM7
- GTIM8
- GTIM9
- GTIM10
param TIM_OCPreload
- TIM_OC_PRE_LOAD_ENABLE
- TIM_OC_PRE_LOAD_DISABLE
return none
void TIM_ConfigOc5Preload(TIM_Module* TIMx, uint32_t TIM_OCPreload)Enables or disables the TIMx peripheral Preload register on CCDAT5.
Source comment
name TIM_ConfigOc5Preload
fun Enables or disables the TIMx peripheral Preload register on CCDAT5.
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
- ATIM3
- GTIM8
- GTIM9
- GTIM10
param TIM_OCPreload
- TIM_OC_PRE_LOAD_ENABLE
- TIM_OC_PRE_LOAD_DISABLE
return none
void TIM_ConfigOc6Preload(TIM_Module* TIMx, uint32_t TIM_OCPreload)Enables or disables the TIMx peripheral Preload register on CCDAT6.
Source comment
name TIM_ConfigOc6Preload
fun Enables or disables the TIMx peripheral Preload register on CCDAT6.
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
- ATIM3
param TIM_OCPreload
- TIM_OC_PRE_LOAD_ENABLE
- TIM_OC_PRE_LOAD_DISABLE
return none
void TIM_ConfigOc7Preload(TIM_Module* TIMx, uint32_t TIM_OCPreload)Enables or disables the TIMx peripheral Preload register on CCDAT6.
Source comment
name TIM_ConfigOc7Preload
fun Enables or disables the TIMx peripheral Preload register on CCDAT6.
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
- ATIM3
param TIM_OCPreload
- TIM_OC_PRE_LOAD_ENABLE
- TIM_OC_PRE_LOAD_DISABLE
return none
void TIM_ConfigOc8Preload(TIM_Module* TIMx, uint32_t TIM_OCPreload)Enables or disables the TIMx peripheral Preload register on CCDAT6.
Source comment
name TIM_ConfigOc8Preload
fun Enables or disables the TIMx peripheral Preload register on CCDAT6.
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
- ATIM3
param TIM_OCPreload
- TIM_OC_PRE_LOAD_ENABLE
- TIM_OC_PRE_LOAD_DISABLE
return none
void TIM_ConfigOc9Preload(TIM_Module* TIMx, uint32_t TIM_OCPreload)Enables or disables the TIMx peripheral Preload register on CCDAT6.
Source comment
name TIM_ConfigOc9Preload
fun Enables or disables the TIMx peripheral Preload register on CCDAT6.
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
- ATIM3
param TIM_OCPreload
- TIM_OC_PRE_LOAD_ENABLE
- TIM_OC_PRE_LOAD_DISABLE
return none
void TIM_ConfigOc1Fast(TIM_Module* TIMx, uint32_t TIM_OCFast)Configures the TIMx Output Compare 1 Fast feature.
Source comment
name TIM_ConfigOc1Fast
fun Configures the TIMx Output Compare 1 Fast feature.
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
- ATIM3
- GTIM1
- GTIM2
- GTIM3
- GTIM4
- GTIM5
- GTIM6
- GTIM7
- GTIM8
- GTIM9
- GTIM10
param TIM_OCPreload
- TIM_OC_FAST_ENABLE
- TIM_OC_FAST_DISABLE
return none
void TIM_ConfigOc2Fast(TIM_Module* TIMx, uint32_t TIM_OCFast)Configures the TIMx Output Compare 2 Fast feature.
Source comment
name TIM_ConfigOc2Fast
fun Configures the TIMx Output Compare 2 Fast feature.
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
- ATIM3
- GTIM1
- GTIM2
- GTIM3
- GTIM4
- GTIM5
- GTIM6
- GTIM7
- GTIM8
- GTIM9
- GTIM10
param TIM_OCPreload
- TIM_OC_FAST_ENABLE
- TIM_OC_FAST_DISABLE
return none
void TIM_ConfigOc3Fast(TIM_Module* TIMx, uint32_t TIM_OCFast)Configures the TIMx Output Compare 3 Fast feature.
Source comment
name TIM_ConfigOc3Fast
fun Configures the TIMx Output Compare 3 Fast feature.
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
- ATIM3
- GTIM1
- GTIM2
- GTIM3
- GTIM4
- GTIM5
- GTIM6
- GTIM7
- GTIM8
- GTIM9
- GTIM10
param TIM_OCPreload
- TIM_OC_FAST_ENABLE
- TIM_OC_FAST_DISABLE
return none
void TIM_ConfigOc4Fast(TIM_Module* TIMx, uint32_t TIM_OCFast)Configures the TIMx Output Compare 4 Fast feature.
Source comment
name TIM_ConfigOc4Fast
fun Configures the TIMx Output Compare 4 Fast feature.
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
- ATIM3
- GTIM1
- GTIM2
- GTIM3
- GTIM4
- GTIM5
- GTIM6
- GTIM7
- GTIM8
- GTIM9
- GTIM10
param TIM_OCPreload
- TIM_OC_FAST_ENABLE
- TIM_OC_FAST_DISABLE
return none
void TIM_ConfigOc5Fast(TIM_Module* TIMx, uint32_t TIM_OCFast)Configures the TIMx Output Compare 5 Fast feature.
Source comment
name TIM_ConfigOc5Fast
fun Configures the TIMx Output Compare 5 Fast feature.
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
- ATIM3
- GTIM8
- GTIM9
- GTIM10
param TIM_OCPreload
- TIM_OC_FAST_ENABLE
- TIM_OC_FAST_DISABLE
return none
void TIM_ConfigOc6Fast(TIM_Module* TIMx, uint32_t TIM_OCFast)Configures the TIMx Output Compare 6 Fast feature.
Source comment
name TIM_ConfigOc6Fast
fun Configures the TIMx Output Compare 6 Fast feature.
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
- ATIM3
param TIM_OCPreload
- TIM_OC_FAST_ENABLE
- TIM_OC_FAST_DISABLE
return none
void TIM_ClrOc1Ref(TIM_Module* TIMx, uint32_t TIM_OCClear)Clears or safeguards the OCREF1 signal on an external event
Source comment
name TIM_ClrOc1Ref
fun Clears or safeguards the OCREF1 signal on an external event
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
- ATIM3
- GTIM1
- GTIM2
- GTIM3
- GTIM4
- GTIM5
- GTIM6
- GTIM7
- GTIM8
- GTIM9
- GTIM10
param TIM_OCPreload
- TIM_OC_CLR_ENABLE
- TIM_OC_CLR_DISABLE
return none
void TIM_ClrOc2Ref(TIM_Module* TIMx, uint32_t TIM_OCClear)Clears or safeguards the OCREF2 signal on an external event
Source comment
name TIM_ClrOc2Ref
fun Clears or safeguards the OCREF2 signal on an external event
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
- ATIM3
- GTIM1
- GTIM2
- GTIM3
- GTIM4
- GTIM5
- GTIM6
- GTIM7
- GTIM8
- GTIM9
- GTIM10
param TIM_OCPreload
- TIM_OC_CLR_ENABLE
- TIM_OC_CLR_DISABLE
return none
void TIM_ClrOc3Ref(TIM_Module* TIMx, uint32_t TIM_OCClear)Clears or safeguards the OCREF3 signal on an external event
Source comment
name TIM_ClrOc3Ref
fun Clears or safeguards the OCREF3 signal on an external event
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
- ATIM3
- GTIM1
- GTIM2
- GTIM3
- GTIM4
- GTIM5
- GTIM6
- GTIM7
- GTIM8
- GTIM9
- GTIM10
param TIM_OCPreload
- TIM_OC_CLR_ENABLE
- TIM_OC_CLR_DISABLE
return none
void TIM_ClrOc4Ref(TIM_Module* TIMx, uint32_t TIM_OCClear)Clears or safeguards the OCREF4 signal on an external event
Source comment
name TIM_ClrOc4Ref
fun Clears or safeguards the OCREF4 signal on an external event
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
- ATIM3
- GTIM1
- GTIM2
- GTIM3
- GTIM4
- GTIM5
- GTIM6
- GTIM7
- GTIM8
- GTIM9
- GTIM10
param TIM_OCPreload
- TIM_OC_CLR_ENABLE
- TIM_OC_CLR_DISABLE
return none
void TIM_ClrOc5Ref(TIM_Module* TIMx, uint32_t TIM_OCClear)Clears or safeguards the OCREF5 signal on an external event
Source comment
name TIM_ClrOc5Ref
fun Clears or safeguards the OCREF5 signal on an external event
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
- ATIM3
- GTIM8
- GTIM9
- GTIM10
param TIM_OCPreload
- TIM_OC_CLR_ENABLE
- TIM_OC_CLR_DISABLE
return none
void TIM_ClrOc6Ref(TIM_Module* TIMx, uint32_t TIM_OCClear)Clears or safeguards the OCREF6 signal on an external event
Source comment
name TIM_ClrOc6Ref
fun Clears or safeguards the OCREF6 signal on an external event
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
- ATIM3
param TIM_OCPreload
- TIM_OC_CLR_ENABLE
- TIM_OC_CLR_DISABLE
return none
void TIM_ClrOcRefInputSource(TIM_Module* TIMx, uint32_t OCRefClearInputSelect,uint32_t OCRefClearInputSource)Set the OCREF clear input source
Source comment
name TIM_ClrOcRefInputSource
fun Set the OCREF clear input source
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
- ATIM3
- GTIM1
- GTIM2
- GTIM3
- GTIM4
- GTIM5
- GTIM6
- GTIM7
- GTIM8
- GTIM9
- GTIM10
param OCRefClearInputSelect
- TIM_ETRSEL
param OCRefClearInputSource
- TIM_CAPETRSEL_0
- TIM_CAPETRSEL_8
- TIM_CAPETRSEL_9
- TIM_CAPETRSEL_10
- TIM_CAPETRSEL_11
- TIM_CAPETRSEL_12
- TIM_CAPETRSEL_13
return none
void TIM_ConfigOc1Polarity(TIM_Module* TIMx, uint32_t OcPolarity)Configures the TIMx channel 1 polarity.
Source comment
name TIM_ConfigOc1Polarity
fun Configures the TIMx channel 1 polarity.
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
- ATIM3
- GTIM1
- GTIM2
- GTIM3
- GTIM4
- GTIM5
- GTIM6
- GTIM7
- GTIM8
- GTIM9
- GTIM10
param TIM_OCPreload
- TIM_OC_POLARITY_HIGH
- TIM_OC_POLARITY_LOW
return none
void TIM_ConfigOc1NPolarity(TIM_Module* TIMx, uint32_t OcNPolarity)Configures the TIMx channel 1N polarity.
Source comment
name TIM_ConfigOc1NPolarity
fun Configures the TIMx channel 1N polarity.
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
- ATIM3
- GTIM8
- GTIM9
- GTIM10
param TIM_OCPreload
- TIM_OCN_POLARITY_HIGH
- TIM_OCN_POLARITY_LOW
return none
void TIM_ConfigOc2Polarity(TIM_Module* TIMx, uint32_t OcPolarity)Configures the TIMx channel 2 polarity.
Source comment
name TIM_ConfigOc2Polarity
fun Configures the TIMx channel 2 polarity.
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
- ATIM3
- GTIM1
- GTIM2
- GTIM3
- GTIM4
- GTIM5
- GTIM6
- GTIM7
- GTIM8
- GTIM9
- GTIM10
param TIM_OCPreload
- TIM_OC_POLARITY_HIGH
- TIM_OC_POLARITY_LOW
return none
void TIM_ConfigOc2NPolarity(TIM_Module* TIMx, uint32_t OcNPolarity)Configures the TIMx channel 2N polarity.
Source comment
name TIM_ConfigOc2NPolarity
fun Configures the TIMx channel 2N polarity.
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
- ATIM3
param TIM_OCPreload
- TIM_OCN_POLARITY_HIGH
- TIM_OCN_POLARITY_LOW
return none
void TIM_ConfigOc3Polarity(TIM_Module* TIMx, uint32_t OcPolarity)Configures the TIMx channel 3 polarity.
Source comment
name TIM_ConfigOc3Polarity
fun Configures the TIMx channel 3 polarity.
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
- ATIM3
- GTIM1
- GTIM2
- GTIM3
- GTIM4
- GTIM5
- GTIM6
- GTIM7
- GTIM8
- GTIM9
- GTIM10
param TIM_OCPreload
- TIM_OC_POLARITY_HIGH
- TIM_OC_POLARITY_LOW
return none
void TIM_ConfigOc3NPolarity(TIM_Module* TIMx, uint32_t OcNPolarity)Configures the TIMx channel 3N polarity.
Source comment
name TIM_ConfigOc3NPolarity
fun Configures the TIMx channel 3N polarity.
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
- ATIM3
param TIM_OCPreload
- TIM_OCN_POLARITY_HIGH
- TIM_OCN_POLARITY_LOW
return none
void TIM_ConfigOc4Polarity(TIM_Module* TIMx, uint32_t OcPolarity)Configures the TIMx channel 4 polarity.
Source comment
name TIM_ConfigOc4Polarity
fun Configures the TIMx channel 4 polarity.
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
- ATIM3
- GTIM1
- GTIM2
- GTIM3
- GTIM4
- GTIM5
- GTIM6
- GTIM7
- GTIM8
- GTIM9
- GTIM10
param TIM_OCPreload
- TIM_OC_POLARITY_HIGH
- TIM_OC_POLARITY_LOW
return none
void TIM_ConfigOc4NPolarity(TIM_Module* TIMx, uint32_t OcNPolarity)Configures the TIMx channel 4N polarity.
Source comment
name TIM_ConfigOc4NPolarity
fun Configures the TIMx channel 4N polarity.
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
- ATIM3
param TIM_OCPreload
- TIM_OCN_POLARITY_HIGH
- TIM_OCN_POLARITY_LOW
return none
void TIM_ConfigOc5Polarity(TIM_Module* TIMx, uint32_t OcPolarity)Configures the TIMx channel 5 polarity.
Source comment
name TIM_ConfigOc5Polarity
fun Configures the TIMx channel 5 polarity.
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
- ATIM3
- GTIM8
- GTIM9
- GTIM10
param TIM_OCPreload
- TIM_OC_POLARITY_HIGH
- TIM_OC_POLARITY_LOW
return none
void TIM_ConfigOc6Polarity(TIM_Module* TIMx, uint32_t OcPolarity)Configures the TIMx channel 6 polarity.
Source comment
name TIM_ConfigOc6Polarity
fun Configures the TIMx channel 6 polarity.
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
- ATIM3
param TIM_OCPreload
- TIM_OC_POLARITY_HIGH
- TIM_OC_POLARITY_LOW
return none
void TIM_EnableCapCmpCh(TIM_Module* TIMx, uint32_t Channel, uint32_t TIM_CCx)Enables or disables the TIM Capture Compare Channel x.
Source comment
name TIM_EnableCapCmpCh
fun Enables or disables the TIM Capture Compare Channel x.
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
- ATIM3
- GTIM1
- GTIM2
- GTIM3
- GTIM4
- GTIM5
- GTIM6
- GTIM7
- GTIM8
- GTIM9
- GTIM10
param Channel
- TIM_CH_1
- TIM_CH_2
- TIM_CH_3
- TIM_CH_4
- TIM_CH_5
- TIM_CH_6
param TIM_CCx
- TIM_CAP_CMP_ENABLE
- TIM_CAP_CMP_DISABLE
return none
void TIM_EnableCapCmpChN(TIM_Module* TIMx, uint32_t Channel, uint32_t TIM_CCxN)Enables or disables the TIM Capture Compare Channel xN.
Source comment
name TIM_EnableCapCmpChN
fun Enables or disables the TIM Capture Compare Channel xN.
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
- ATIM3
- GTIM8
- GTIM9
- GTIM10
param Channel
- TIM_CH_1
- TIM_CH_2
- TIM_CH_3
- TIM_CH_4
param TIM_CCx
- TIM_CAP_CMP_N_ENABLE
- TIM_CAP_CMP_N_DISABLE
return none
void TIM_SelectOcMode(TIM_Module* TIMx, uint32_t Channel, uint32_t OcMode)Selects the TIM Output Compare Mode.
Source comment
name TIM_SelectOcMode
fun Selects the TIM Output Compare Mode.
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
- ATIM3
- GTIM1
- GTIM2
- GTIM3
- GTIM4
- GTIM5
- GTIM6
- GTIM7
- GTIM8
- GTIM9
- GTIM10
param Channel
- TIM_CH_1
- TIM_CH_2
- TIM_CH_3
- TIM_CH_4
- TIM_CH_5
- TIM_CH_6
param OcMode
- TIM_OCMODE_TIMING
- TIM_OCMODE_ACTIVE
- TIM_OCMODE_INACTIVE
- TIM_OCMODE_TOGGLE
- TIM_OCMODE_PWM1
- TIM_OCMODE_PWM2
- TIM_FORCED_ACTION_ACTIVE
- TIM_FORCED_ACTION_INACTIVE
- TIM_OCMODE_OPMOD_RETRIG1
- TIM_OCMODE_OPMOD_RETRIG2
- TIM_OCMODE_COMBI_PWM1
- TIM_OCMODE_COMBI_PWM2
return none
void TIM_EnableUpdateEvt(TIM_Module* TIMx, FunctionalState Cmd)Enables or Disables the TIMx Update event bit.
Source comment
name TIM_EnableUpdateEvt
fun Enables or Disables the TIMx Update event bit.
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
- ATIM3
- GTIM1
- GTIM2
- GTIM3
- GTIM4
- GTIM5
- GTIM6
- GTIM7
- GTIM8
- GTIM9
- GTIM10
- BTIM1
- BTIM2
param Cmd
- ENABLE
- DISABLE
return none
void TIM_ConfigUpdateEvt(TIM_Module* TIMx, FunctionalState Cmd)Enables or Disables the TIMx Update event.
Source comment
name TIM_ConfigUpdateEvt
fun Enables or Disables the TIMx Update event.
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
- ATIM3
- GTIM1
- GTIM2
- GTIM3
- GTIM4
- GTIM5
- GTIM6
- GTIM7
- GTIM8
- GTIM9
- GTIM10
- BTIM1
- BTIM2
param Cmd
- ENABLE
- DISABLE
return none
void TIM_ConfigUpdateRequestIntSrc(TIM_Module* TIMx, uint32_t TIM_UpdateSource)Configures the TIMx Update Request Interrupt source.
Source comment
name TIM_ConfigUpdateRequestIntSrc
fun Configures the TIMx Update Request Interrupt source.
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
- ATIM3
- GTIM1
- GTIM2
- GTIM3
- GTIM4
- GTIM5
- GTIM6
- GTIM7
- GTIM8
- GTIM9
- GTIM10
- BTIM1
- BTIM2
param TIM_UpdateSource
- TIM_UPDATE_SRC_GLOBAL
- TIM_UPDATE_SRC_REGULAR
return none
void TIM_SelectHallSensor(TIM_Module* TIMx, FunctionalState Cmd)Enables or disables the TIMx’s Hall sensor interface.
Source comment
name TIM_SelectHallSensor
fun Enables or disables the TIMx's Hall sensor interface.
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
- ATIM3
- GTIM1
- GTIM2
- GTIM3
- GTIM4
- GTIM5
- GTIM6
- GTIM7
- GTIM8
- GTIM9
- GTIM10
param Cmd
- ENABLE
- DISABLE
return none
void TIM_SelectOnePulseMode(TIM_Module* TIMx, uint32_t TIM_OPMode)Selects the TIMx’s One Pulse Mode.
Source comment
name TIM_SelectOnePulseMode
fun Selects the TIMx's One Pulse Mode.
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
- ATIM3
- GTIM1
- GTIM2
- GTIM3
- GTIM4
- GTIM5
- GTIM6
- GTIM7
- GTIM8
- GTIM9
- GTIM10
param TIM_OPMode
- TIM_OPMODE_SINGLE
- TIM_OPMODE_REPET
return none
void TIM_SelectOutputTrig(TIM_Module* TIMx, uint32_t TIM_TRGOSource)Selects the TIMx Trigger Output Mode.
Source comment
name TIM_SelectOutputTrig
fun Selects the TIMx Trigger Output Mode.
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
- ATIM3
- GTIM1
- GTIM2
- GTIM3
- GTIM4
- GTIM5
- GTIM6
- GTIM7
- GTIM8
- GTIM9
- GTIM10
- BTIM1
- BTIM2
param TIM_TRGOSource
- TIM_TRGO_SRC_RESET
- TIM_TRGO_SRC_ENABLE
- TIM_TRGO_SRC_UPDATE
- TIM_TRGO_SRC_OC1
- TIM_TRGO_SRC_OC1REF
- TIM_TRGO_SRC_OC2REF
- TIM_TRGO_SRC_OC3REF
- TIM_TRGO_SRC_OC4REF
- TIM_TRGO_SRC_OC4_7_8_9REF
return none
void TIM_SelectOutputTrig2(TIM_Module* TIMx, uint32_t TIM_TRGO2Source)Selects the TIMx Trigger Output Mode.
Source comment
name TIM_SelectOutputTrig2
fun Selects the TIMx Trigger Output Mode.
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
- ATIM3
param TIM_TRGO2Source
- TIM_TRGO2_SRC_RESET
- TIM_TRGO2_SRC_ENABLE
- TIM_TRGO2_SRC_UPDATE
- TIM_TRGO2_SRC_OC1
- TIM_TRGO2_SRC_OC1REF
- TIM_TRGO2_SRC_OC2REF
- TIM_TRGO2_SRC_OC3REF
- TIM_TRGO2_SRC_OC4REF
- TIM_TRGO2_SRC_OC5REF
- TIM_TRGO2_SRC_OC6REF
- LL_TIM_TRGO2_OC4_RISINGFALLING
- LL_TIM_TRGO2_OC6_RISINGFALLING
- LL_TIM_TRGO2_OC4_RISING_OC6_RISING
- LL_TIM_TRGO2_OC4_RISING_OC6_FALLING
- LL_TIM_TRGO2_OC5_RISING_OC6_RISING
- LL_TIM_TRGO2_OC5_RISING_OC6_FALLING
return none
void TIM_SelectSlaveMode(TIM_Module* TIMx, uint32_t TIM_SlaveMode)Selects the TIMx Slave Mode.
Source comment
name TIM_SelectSlaveMode
fun Selects the TIMx Slave Mode.
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
- ATIM3
- GTIM1
- GTIM2
- GTIM3
- GTIM4
- GTIM5
- GTIM6
- GTIM7
- GTIM8
- GTIM9
- GTIM10
param TIM_SlaveMode
- TIM_SLAVE_MODE_DISABLE
- TIM_SLAVE_MODE_RESET
- TIM_SLAVE_MODE_GATED
- TIM_SLAVE_MODE_TRIG
- TIM_SLAVE_MODE_EXT1
- TIM_SLAVE_MODE_GATED_RESET
- TIM_SLAVE_MODE_TRIG_RESET
return none
void TIM_SelectMasterSlaveMode(TIM_Module* TIMx, uint32_t TIM_MasterSlaveMode)Sets or Resets the TIMx Master/Slave Mode.
Source comment
name TIM_SelectMasterSlaveMode
fun Sets or Resets the TIMx Master/Slave Mode.
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
- ATIM3
- GTIM1
- GTIM2
- GTIM3
- GTIM4
- GTIM5
- GTIM6
- GTIM7
- GTIM8
- GTIM9
- GTIM10
param TIM_SlaveMode
- TIM_MASTER_SLAVE_MODE_ENABLE
- TIM_MASTER_SLAVE_MODE_DISABLE
return none
void TIM_SetCnt(TIM_Module* TIMx, uint32_t Counter)Sets the TIMx Counter Register value
Source comment
name TIM_SetCnt
fun Sets the TIMx Counter Register value
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
- ATIM3
- GTIM1
- GTIM2
- GTIM3
- GTIM4
- GTIM5
- GTIM6
- GTIM7
- GTIM8
- GTIM9
- GTIM10
- BTIM1
- BTIM2
param Counter
- Counter can be a number between 0x00000000 and 0xFFFFFFFF
return none
void TIM_SetAutoReload(TIM_Module* TIMx, uint32_t Autoreload)Sets the TIMx Autoreload Register value
Source comment
name TIM_SetAutoReload
fun Sets the TIMx Autoreload Register value
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
- ATIM3
- GTIM1
- GTIM2
- GTIM3
- GTIM4
- GTIM5
- GTIM6
- GTIM7
- GTIM8
- GTIM9
- GTIM10
- BTIM1
- BTIM2
param Autoreload
- Autoreload can be a number between 0x00000000 and 0xFFFFFFFF
return none
void TIM_SetCmp1(TIM_Module* TIMx, uint32_t Compare1)Sets the TIMx Capture Compare1 Register value
Source comment
name TIM_SetCmp1
fun Sets the TIMx Capture Compare1 Register value
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
- ATIM3
- GTIM1
- GTIM2
- GTIM3
- GTIM4
- GTIM5
- GTIM6
- GTIM7
- GTIM8
- GTIM9
- GTIM10
param Compare1
- GTIM1 and GTIM4 range from 0x00000000 to 0xffffffff, but the others range from 0x0000 to 0xffff.
return none
void TIM_SetCmp2(TIM_Module* TIMx, uint32_t Compare2)Sets the TIMx Capture Compare2 Register value
Source comment
name TIM_SetCmp2
fun Sets the TIMx Capture Compare2 Register value
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
- ATIM3
- GTIM1
- GTIM2
- GTIM3
- GTIM4
- GTIM5
- GTIM6
- GTIM7
- GTIM8
- GTIM9
- GTIM10
param Compare2
- GTIM1 and GTIM4 range from 0x00000000 to 0xffffffff, but the others range from 0x0000 to 0xffff.
return none
void TIM_SetCmp3(TIM_Module* TIMx, uint32_t Compare3)Sets the TIMx Capture Compare3 Register value
Source comment
name TIM_SetCmp3
fun Sets the TIMx Capture Compare3 Register value
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
- ATIM3
- GTIM1
- GTIM2
- GTIM3
- GTIM4
- GTIM5
- GTIM6
- GTIM7
- GTIM8
- GTIM9
- GTIM10
param Compare3
- GTIM1 and GTIM4 range from 0x00000000 to 0xffffffff, but the others range from 0x0000 to 0xffff.
return none
void TIM_SetCmp4(TIM_Module* TIMx, uint32_t Compare4)Sets the TIMx Capture Compare4 Register value
Source comment
name TIM_SetCmp4
fun Sets the TIMx Capture Compare4 Register value
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
- ATIM3
- GTIM1
- GTIM2
- GTIM3
- GTIM4
- GTIM5
- GTIM6
- GTIM7
- GTIM8
- GTIM9
- GTIM10
param Compare4
- GTIM1 and GTIM4 range from 0x00000000 to 0xffffffff, but the others range from 0x0000 to 0xffff.
return none
void TIM_SetCmp5(TIM_Module* TIMx, uint16_t Compare5)Sets the TIMx Capture Compare5 Register value
Source comment
name TIM_SetCmp5
fun Sets the TIMx Capture Compare5 Register value
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
- ATIM3
- GTIM8
- GTIM9
- GTIM10
param Compare5
- Compare5 can be a number between 0x0000 and 0xFFFF
return none
void TIM_SetCmp6(TIM_Module* TIMx, uint16_t Compare6)Sets the TIMx Capture Compare6 Register value
Source comment
name TIM_SetCmp6
fun Sets the TIMx Capture Compare6 Register value
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
- ATIM3
param Compare6
- Compare6 can be a number between 0x0000 and 0xFFFF
return none
void TIM_SetCmp7(TIM_Module* TIMx, uint16_t Compare7)Sets the TIMx Capture Compare7 Register value
Source comment
name TIM_SetCmp7
fun Sets the TIMx Capture Compare7 Register value
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
- ATIM3
param Compare7
- Compare7 can be a number between 0x0000 and 0xFFFF
return none
void TIM_SetCmp8(TIM_Module* TIMx, uint16_t Compare8)Sets the TIMx Capture Compare8 Register value
Source comment
name TIM_SetCmp8
fun Sets the TIMx Capture Compare8 Register value
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
- ATIM3
param Compare8
- Compare8 can be a number between 0x0000 and 0xFFFF
return none
void TIM_SetCmp9(TIM_Module* TIMx, uint16_t Compare9)Sets the TIMx Capture Compare9 Register value
Source comment
name TIM_SetCmp9
fun Sets the TIMx Capture Compare9 Register value
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
- ATIM3
param Compare9
- Compare9 can be a number between 0x0000 and 0xFFFF
return none
void TIM_SetCmp1D(TIM_Module* TIMx, uint16_t compare1D)Sets the CCDDAT1[16:31] in TIM1_CCDAT1 register
Source comment
name TIM_SetCmp1D
fun Sets the CCDDAT1[16:31] in TIM1_CCDAT1 register
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
- ATIM3
param compare1D
- compare1D can be a number between 0x0000 and 0xFFFF
return none
void TIM_SetCmp2D(TIM_Module* TIMx, uint16_t compare2D)Sets the CCDDAT2[16:31] in TIM1_CCDAT2 register
Source comment
name TIM_SetCmp2D
fun Sets the CCDDAT2[16:31] in TIM1_CCDAT2 register
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
- ATIM3
param compare2D
- compare2D can be a number between 0x0000 and 0xFFFF
return none
void TIM_SetCmp3D(TIM_Module* TIMx, uint16_t compare3D)Sets the CCDDAT3[16:31] in TIM1_CCDAT3 register
Source comment
name TIM_SetCmp3D
fun Sets the CCDDAT3[16:31] in TIM1_CCDAT3 register
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
- ATIM3
param compare3D
- compare3D can be a number between 0x0000 and 0xFFFF
return none
void TIM_SetCmp4D(TIM_Module* TIMx, uint16_t compare4D)Sets the CCDDAT4[16:31] in TIM1_CCDAT4 register
Source comment
name TIM_SetCmp4D
fun Sets the CCDDAT4[16:31] in TIM1_CCDAT4 register
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
- ATIM3
param compare4D
- compare4D can be a number between 0x0000 and 0xFFFF
return none
void ConfigTI1(TIM_Module* TIMx, uint32_t ICPolarity, uint32_t ICSelection, uint32_t ICFilter)Configure the TI1 as Input.
Source comment
name ConfigTI1
fun Configure the TI1 as Input.
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
- ATIM3
- GTIM1
- GTIM2
- GTIM3
- GTIM4
- GTIM5
- GTIM6
- GTIM7
- GTIM8
- GTIM9
- GTIM10
param ICPolarity
- TIM_IC_POLARITY_RISING
- TIM_IC_POLARITY_FALLING
param ICSelection
- TIM_IC_SELECTION_DIRECTTI
- TIM_IC_SELECTION_INDIRECTTI
- TIM_IC_SELECTION_TRC
param ICFilter
- ICFilter can be a number between 0x0 and 0xF
return none
void ConfigTI2(TIM_Module* TIMx, uint32_t ICPolarity, uint32_t ICSelection, uint32_t ICFilter)Configure the TI2 as Input.
Source comment
name ConfigTI2
fun Configure the TI2 as Input.
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
- ATIM3
- GTIM1
- GTIM2
- GTIM3
- GTIM4
- GTIM5
- GTIM6
- GTIM7
- GTIM8
- GTIM9
- GTIM10
param ICPolarity
- TIM_IC_POLARITY_RISING
- TIM_IC_POLARITY_FALLING
param ICSelection
- TIM_IC_SELECTION_DIRECTTI
- TIM_IC_SELECTION_INDIRECTTI
- TIM_IC_SELECTION_TRC
param ICFilter
- ICFilter can be a number between 0x0 and 0xF
return none
void ConfigTI3(TIM_Module* TIMx, uint32_t ICPolarity, uint32_t ICSelection, uint32_t ICFilter)Configure the TI3 as Input.
Source comment
name ConfigTI3
fun Configure the TI3 as Input.
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
- ATIM3
- GTIM1
- GTIM2
- GTIM3
- GTIM4
- GTIM5
- GTIM6
- GTIM7
- GTIM8
- GTIM9
- GTIM10
param ICPolarity
- TIM_IC_POLARITY_RISING
- TIM_IC_POLARITY_FALLING
param ICSelection
- TIM_IC_SELECTION_DIRECTTI
- TIM_IC_SELECTION_INDIRECTTI
- TIM_IC_SELECTION_TRC
param ICFilter
- ICFilter can be a number between 0x0 and 0xF
return none
void ConfigTI4(TIM_Module* TIMx, uint32_t ICPolarity, uint32_t ICSelection, uint32_t ICFilter)Configure the TI4 as Input.
Source comment
name ConfigTI4
fun Configure the TI4 as Input.
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
- ATIM3
- GTIM1
- GTIM2
- GTIM3
- GTIM4
- GTIM5
- GTIM6
- GTIM7
- GTIM8
- GTIM9
- GTIM10
param ICPolarity
- TIM_IC_POLARITY_RISING
- TIM_IC_POLARITY_FALLING
param ICSelection
- TIM_IC_SELECTION_DIRECTTI
- TIM_IC_SELECTION_INDIRECTTI
- TIM_IC_SELECTION_TRC
param ICFilter
- ICFilter can be a number between 0x0 and 0xF
return none
void TIM_SetInCap1Prescaler(TIM_Module* TIMx, uint32_t ICPrescaler)Sets the TIMx Input Capture 1 prescaler.
Source comment
name TIM_SetInCap1Prescaler
fun Sets the TIMx Input Capture 1 prescaler.
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
- ATIM3
- GTIM1
- GTIM2
- GTIM3
- GTIM4
- GTIM5
- GTIM6
- GTIM7
- GTIM8
- GTIM9
- GTIM10
param ICPrescaler
- TIM_IC_PSC_DIV1
- TIM_IC_PSC_DIV2
- TIM_IC_PSC_DIV4
- TIM_IC_PSC_DIV8
return none
void TIM_SetInCap2Prescaler(TIM_Module* TIMx, uint32_t ICPrescaler)Sets the TIMx Input Capture 2 prescaler.
Source comment
name TIM_SetInCap2Prescaler
fun Sets the TIMx Input Capture 2 prescaler.
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
- ATIM3
- GTIM1
- GTIM2
- GTIM3
- GTIM4
- GTIM5
- GTIM6
- GTIM7
- GTIM8
- GTIM9
- GTIM10
param ICPrescaler
- TIM_IC_PSC_DIV1
- TIM_IC_PSC_DIV2
- TIM_IC_PSC_DIV4
- TIM_IC_PSC_DIV8
return none
void TIM_SetInCap3Prescaler(TIM_Module* TIMx, uint32_t ICPrescaler)Sets the TIMx Input Capture 3 prescaler.
Source comment
name TIM_SetInCap3Prescaler
fun Sets the TIMx Input Capture 3 prescaler.
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
- ATIM3
- GTIM1
- GTIM2
- GTIM3
- GTIM4
- GTIM5
- GTIM6
- GTIM7
- GTIM8
- GTIM9
- GTIM10
param ICPrescaler
- TIM_IC_PSC_DIV1
- TIM_IC_PSC_DIV2
- TIM_IC_PSC_DIV4
- TIM_IC_PSC_DIV8
return none
void TIM_SetInCap4Prescaler(TIM_Module* TIMx, uint32_t ICPrescaler)Sets the TIMx Input Capture 4 prescaler.
Source comment
name TIM_SetInCap4Prescaler
fun Sets the TIMx Input Capture 4 prescaler.
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
- ATIM3
- GTIM1
- GTIM2
- GTIM3
- GTIM4
- GTIM5
- GTIM6
- GTIM7
- GTIM8
- GTIM9
- GTIM10
param ICPrescaler
- TIM_IC_PSC_DIV1
- TIM_IC_PSC_DIV2
- TIM_IC_PSC_DIV4
- TIM_IC_PSC_DIV8
return none
void TIM_SelectInputTrig(TIM_Module* TIMx, uint32_t TIM_InputTriggerSource)Selects the Input Trigger source
Source comment
name TIM_SelectInputTrig
fun Selects the Input Trigger source
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
- ATIM3
- GTIM1
- GTIM2
- GTIM3
- GTIM4
- GTIM5
- GTIM6
- GTIM7
- GTIM8
- GTIM9
- GTIM10
param TIM_InputTriggerSource:
- TIM_TRIG_SEL_IN_TR0
- TIM_TRIG_SEL_IN_TR1
- TIM_TRIG_SEL_IN_TR2
- TIM_TRIG_SEL_IN_TR3
- TIM_TRIG_SEL_IN_TR4
- TIM_TRIG_SEL_IN_TR5
- TIM_TRIG_SEL_IN_TR6
- TIM_TRIG_SEL_IN_TR7
- TIM_TRIG_SEL_IN_TR8
- TIM_TRIG_SEL_IN_TR9
- TIM_TRIG_SEL_IN_TR10
- TIM_TRIG_SEL_IN_TR11
- TIM_TRIG_SEL_IN_TR12
- TIM_TRIG_SEL_IN_TR13
- TIM_TRIG_SEL_IN_TR14
- TIM_TRIG_SEL_TI1F_ED
- TIM_TRIG_SEL_TI1FP1
- TIM_TRIG_SEL_TI2FP2
- TIM_TRIG_SEL_ETRF
return none
void TIM_ConfigExtTrig(TIM_Module* TIMx,uint32_t TIM_ExtTRGPrescaler,uint32_t TIM_ExtTRGPolarity,uint32_t ExtTRGFilter)Configures the TIMx External Trigger (ETR).
Source comment
name TIM_ConfigExtTrig
fun Configures the TIMx External Trigger (ETR).
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
- ATIM3
- GTIM1
- GTIM2
- GTIM3
- GTIM4
- GTIM5
- GTIM6
- GTIM7
- GTIM8
- GTIM9
- GTIM10
param TIM_ExtTRGPrescaler:
- TIM_EXT_TRG_PSC_OFF
- TIM_EXT_TRG_PSC_DIV2
- TIM_EXT_TRG_PSC_DIV4
- TIM_EXT_TRG_PSC_DIV8
param TIM_ExtTRGPolarity
- TIM_EXT_TRIG_POLARITY_INVERTED
- TIM_EXT_TRIG_POLARITY_NONINVERTED
param ExtTRGFilter
- ExtTRGFilter can be a number between 0x0 and 0xF
return none
void TIM_SelectETRInputSource(TIM_Module* TIMx, uint32_t TIM_ETRInputSource)Configures the source of tim_etr_in.
Source comment
name TIM_SelectETRInputSource
fun Configures the source of tim_etr_in.
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
- ATIM3
- GTIM1
- GTIM2
- GTIM3
- GTIM4
- GTIM5
- GTIM6
- GTIM7
- GTIM8
- GTIM9
- GTIM10
param TIM_ETRInputSource:
- TIM_CAPETRSEL_0
- TIM_CAPETRSEL_8
- TIM_CAPETRSEL_10
- TIM_CAPETRSEL_11
- TIM_CAPETRSEL_12
- TIM_CAPETRSEL_13
return none
void TIM_SetClkDiv(TIM_Module* TIMx, uint32_t TIM_CKD)Sets the TIMx Clock Division value.
Source comment
name TIM_SetClkDiv
fun Sets the TIMx Clock Division value.
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
- ATIM3
- GTIM1
- GTIM2
- GTIM3
- GTIM4
- GTIM5
- GTIM6
- GTIM7
- GTIM8
- GTIM9
- GTIM10
param TIM_CKD:
- TIM_CLK_DIV1
- TIM_CLK_DIV2
- TIM_CLK_DIV4
return none
uint32_t TIM_GetCap1(TIM_Module* TIMx)Gets the TIMx Input Capture 1 value.
Source comment
name TIM_GetCap1
fun Gets the TIMx Input Capture 1 value.
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
- ATIM3
- GTIM1
- GTIM2
- GTIM3
- GTIM4
- GTIM5
- GTIM6
- GTIM7
- GTIM8
- GTIM9
- GTIM10
return Capture Compare 1 Register value.
uint32_t TIM_GetCap2(TIM_Module* TIMx)Gets the TIMx Input Capture 2 value.
Source comment
name TIM_GetCap2
fun Gets the TIMx Input Capture 2 value.
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
- ATIM3
- GTIM1
- GTIM2
- GTIM3
- GTIM4
- GTIM5
- GTIM6
- GTIM7
- GTIM8
- GTIM9
- GTIM10
return Capture Compare 2 Register value.
uint32_t TIM_GetCap3(TIM_Module* TIMx)Gets the TIMx Input Capture 3 value.
Source comment
name TIM_GetCap3
fun Gets the TIMx Input Capture 3 value.
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
- ATIM3
- GTIM1
- GTIM2
- GTIM3
- GTIM4
- GTIM5
- GTIM6
- GTIM7
- GTIM8
- GTIM9
- GTIM10
return Capture Compare 3 Register value.
uint32_t TIM_GetCap4(TIM_Module* TIMx)Gets the TIMx Input Capture 4 value.
Source comment
name TIM_GetCap4
fun Gets the TIMx Input Capture 4 value.
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
- ATIM3
- GTIM1
- GTIM2
- GTIM3
- GTIM4
- GTIM5
- GTIM6
- GTIM7
- GTIM8
- GTIM9
- GTIM10
return Capture Compare 4 Register value.
uint16_t TIM_GetCap5(TIM_Module* TIMx)Gets the TIMx Input Capture 5 value.
Source comment
name TIM_GetCap5
fun Gets the TIMx Input Capture 5 value.
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
- ATIM3
- GTIM8
- GTIM9
- GTIM10
return Capture Compare 5 Register value.
uint16_t TIM_GetCap6(TIM_Module* TIMx)Gets the TIMx Input Capture 6 value.
Source comment
name TIM_GetCap6
fun Gets the TIMx Input Capture 6 value.
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
- ATIM3
return Capture Compare 6 Register value.
uint16_t TIM_GetCap7(TIM_Module* TIMx)Gets the TIMx Input Capture 7 value.
Source comment
name TIM_GetCap7
fun Gets the TIMx Input Capture 7 value.
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
- ATIM3
return Capture Compare 7 Register value.
uint16_t TIM_GetCap8(TIM_Module* TIMx)Gets the TIMx Input Capture 8 value.
Source comment
name TIM_GetCap8
fun Gets the TIMx Input Capture 8 value.
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
- ATIM3
return Capture Compare 8 Register value.
uint16_t TIM_GetCap9(TIM_Module* TIMx)Gets the TIMx Input Capture 9 value.
Source comment
name TIM_GetCap9
fun Gets the TIMx Input Capture 9 value.
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
- ATIM3
return Capture Compare 9 Register value.
uint16_t TIM_GetCap1D(TIM_Module* TIMx)Gets the TIMx Input Capture 1D value.
Source comment
name TIM_GetCap1D
fun Gets the TIMx Input Capture 1D value.
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
- ATIM3
return Capture Compare 1D Register value.
uint16_t TIM_GetCap2D(TIM_Module* TIMx)Gets the TIMx Input Capture 2D value.
Source comment
name TIM_GetCap2D
fun Gets the TIMx Input Capture 2D value.
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
- ATIM3
return Capture Compare 2D Register value.
uint16_t TIM_GetCap3D(TIM_Module* TIMx)Gets the TIMx Input Capture 3D value.
Source comment
name TIM_GetCap3D
fun Gets the TIMx Input Capture 3D value.
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
- ATIM3
return Capture Compare 3D Register value.
uint16_t TIM_GetCap4D(TIM_Module* TIMx)Gets the TIMx Input Capture 4D value.
Source comment
name TIM_GetCap4D
fun Gets the TIMx Input Capture 4D value.
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
- ATIM3
return Capture Compare 4D Register value.
uint32_t TIM_GetCnt(TIM_Module* TIMx)Gets the TIMx Counter value.
Source comment
name TIM_GetCnt
fun Gets the TIMx Counter value.
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
- ATIM3
- GTIM1
- GTIM2
- GTIM3
- GTIM4
- GTIM5
- GTIM6
- GTIM7
- GTIM8
- GTIM9
- GTIM10
- BTIM1
- BTIM2
return Counter Register value.
uint16_t TIM_GetPrescaler(TIM_Module* TIMx)Gets the TIMx Prescaler value.
Source comment
name TIM_GetPrescaler
fun Gets the TIMx Prescaler value.
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
- ATIM3
- GTIM1
- GTIM2
- GTIM3
- GTIM4
- GTIM5
- GTIM6
- GTIM7
- GTIM8
- GTIM9
- GTIM10
- BTIM1
- BTIM2
return Prescaler Register value.
uint32_t TIM_GetAutoReload(TIM_Module* TIMx)Gets the TIMx AR value.
Source comment
name TIM_GetAutoReload
fun Gets the TIMx AR value.
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
- ATIM3
- GTIM1
- GTIM2
- GTIM3
- GTIM4
- GTIM5
- GTIM6
- GTIM7
- GTIM8
- GTIM9
- GTIM10
- BTIM1
- BTIM2
return AR Register value.
FlagStatus TIM_GetCCENStatus(TIM_Module* TIMx, uint32_t TIM_CCEN)Checks whether the specified TIM flag is set or not.
Source comment
name TIM_GetCCENStatus
fun Checks whether the specified TIM flag is set or not.
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
- ATIM3
- GTIM1
- GTIM2
- GTIM3
- GTIM4
- GTIM5
- GTIM6
- GTIM7
- GTIM8
- GTIM9
- GTIM10
param TIM_CCEN :
- TIM_CC1EN
- TIM_CC1NEN
- TIM_CC2EN
- TIM_CC2NEN
- TIM_CC3EN
- TIM_CC3NEN
- TIM_CC4EN
- TIM_CC4NEN
- TIM_CC5EN
- TIM_CC6EN
return The new state of TIM_FLAG (SET or RESET).
FlagStatus TIM_GetFlagStatus(TIM_Module* TIMx, uint32_t TIM_FLAG)Checks whether the specified TIM flag is set or not.
Source comment
name TIM_GetFlagStatus
fun Checks whether the specified TIM flag is set or not.
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
- ATIM3
- GTIM1
- GTIM2
- GTIM3
- GTIM4
- GTIM5
- GTIM6
- GTIM7
- GTIM8
- GTIM9
- GTIM10
- BTIM1
- BTIM2
param TIM_FLAG :
- TIM_FLAG_UPDATE
- TIM_FLAG_CC1
- TIM_FLAG_CC2
- TIM_FLAG_CC3
- TIM_FLAG_CC4
- TIM_FLAG_CC5
- TIM_FLAG_CC6
- TIM_FLAG_CC7
- TIM_FLAG_CC8
- TIM_FLAG_CC9
- TIM_FLAG_COM
- TIM_FLAG_TRIG
- TIM_FLAG_BREAK
- TIM_FLAG_BREAK2
- TIM_FLAG_SYS_BREAK
- TIM_FLAG_CC1OF
- TIM_FLAG_CC2OF
- TIM_FLAG_CC3OF
- TIM_FLAG_CC4OF
return The new state of TIM_FLAG (SET or RESET).
void TIM_ClearFlag(TIM_Module* TIMx, uint32_t TIM_FLAG)Clears the TIMx’s pending flags.
Source comment
name TIM_ClearFlag
fun Clears the TIMx's pending flags.
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
- ATIM3
- GTIM1
- GTIM2
- GTIM3
- GTIM4
- GTIM5
- GTIM6
- GTIM7
- GTIM8
- GTIM9
- GTIM10
- BTIM1
- BTIM2
param TIM_FLAG :
- TIM_FLAG_UPDATE
- TIM_FLAG_CC1
- TIM_FLAG_CC2
- TIM_FLAG_CC3
- TIM_FLAG_CC4
- TIM_FLAG_CC5
- TIM_FLAG_CC6
- TIM_FLAG_CC7
- TIM_FLAG_CC8
- TIM_FLAG_CC9
- TIM_FLAG_COM
- TIM_FLAG_TRIG
- TIM_FLAG_BREAK
- TIM_FLAG_BREAK2
- TIM_FLAG_SYS_BREAK
- TIM_FLAG_CC1OF
- TIM_FLAG_CC2OF
- TIM_FLAG_CC3OF
- TIM_FLAG_CC4OF
return none.
INTStatus TIM_GetIntStatus(TIM_Module* TIMx, uint32_t TIM_IT)Checks whether the TIM interrupt has occurred or not.
Source comment
name TIM_GetIntStatus
fun Checks whether the TIM interrupt has occurred or not.
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
- ATIM3
- GTIM1
- GTIM2
- GTIM3
- GTIM4
- GTIM5
- GTIM6
- GTIM7
- GTIM8
- GTIM9
- GTIM10
- BTIM1
- BTIM2
param TIM_IT :
- TIM_INT_UPDATE
- TIM_INT_CC1
- TIM_INT_CC2
- TIM_INT_CC3
- TIM_INT_CC4
- TIM_INT_CC5
- TIM_INT_CC6
- TIM_INT_CC7
- TIM_INT_CC8
- TIM_INT_CC9
- TIM_INT_COM
- TIM_INT_TRIG
- TIM_INT_BREAK
- TIM_INT_BREAK2
- TIM_INT_SYS_BREAK
return The new state of the TIM_IT(SET or RESET).
void TIM_ClrIntPendingBit(TIM_Module* TIMx, uint32_t TIM_IT)Clears the TIMx’s interrupt pending bits.
Source comment
name TIM_ClrIntPendingBit
fun Clears the TIMx's interrupt pending bits.
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
- ATIM3
- GTIM1
- GTIM2
- GTIM3
- GTIM4
- GTIM5
- GTIM6
- GTIM7
- GTIM8
- GTIM9
- GTIM10
- BTIM1
- BTIM2
param TIM_IT :
- TIM_INT_UPDATE
- TIM_INT_CC1
- TIM_INT_CC2
- TIM_INT_CC3
- TIM_INT_CC4
- TIM_INT_CC5
- TIM_INT_CC6
- TIM_INT_CC7
- TIM_INT_CC8
- TIM_INT_CC9
- TIM_INT_COM
- TIM_INT_TRIG
- TIM_INT_BREAK
- TIM_INT_BREAK2
- TIM_INT_SYS_BREAK
return none.
void TIM_SelectCenterAlignTrig(TIM_Module* TIMx, uint32_t TIM_CenterAlignTriggerSource)Setting the trigger mode in central alignment mode.
Source comment
name TIM_SelectCenterAlignTrig.
fun Setting the trigger mode in central alignment mode.
param TIMx:
- ATIM1
- ATIM2
- ATIM3
param TIM_CenterAlignTriggerSource
- TIM_UP_COUNTING
- TIM_DOWN_COUNTING
- TIM_UP_DOWN_COUNTING
return none
void TIM_AsymmetricEnable(TIM_Module* TIMx, FunctionalState Cmd)Enable or disable asymmetric mode in center-aligned.
Source comment
name TIM_Asymmetric_Enable.
fun Enable or disable asymmetric mode in center-aligned.
param TIMx:
- ATIM1
- ATIM2
- ATIM3
- BTIM8
- BTIM9
- BTIM10
param Cmd
- ENABLE
- DISABLE
return none
Use note: n32h49x_tim.h declares it as TIM_AsymmetricEnable on line 879, while the comment directly above the implementation in n32h49x_tim.c reads TIM_Asymmetric_Enable.; call it by the name in the header, TIM_AsymmetricEnable.
void TIM_OCxRefTriggerADC(TIM_Module* TIMx, uint32_t OCxRef, FunctionalState Cmd)Enable or disable OCxREF to trigger ADC(x = 4,7,8 or 9).
Source comment
name TIM_OCxRefTriggerADC.
fun Enable or disable OCxREF to trigger ADC(x = 4,7,8 or 9).
param TIMx:
- ATIM1
- ATIM2
- ATIM3
param OCxRef
- TIM_CTRL2_TRIG4
- TIM_CTRL2_TRIG7
- TIM_CTRL2_TRIG8
- TIM_CTRL2_TRIG9
param Cmd
- ENABLE
- DISABLE
return none
void TIM_IC1FiltConfig(TIM_Module* TIMx, TIM_FiltInitType* TIM_FiltInitStruct)Config the filter of channel1.
Source comment
name TIM_IC1FiltConfig
fun Config the filter of channel1.
param TIMx:
- GTIM1
- GTIM2
- GTIM3
- GTIM4
- GTIM5
- GTIM6
- GTIM7
- GTIM8
- GTIM9
- GTIM10
param TIM_FiltInitStruct:
- refer to the definition of TIM_FiltInitType
return none
void TIM_IC2FiltConfig(TIM_Module* TIMx, TIM_FiltInitType* TIM_FiltInitStruct)Config the filter of channel2.
Source comment
name TIM_IC2FiltConfig
fun Config the filter of channel2.
param TIMx:
- GTIM1
- GTIM2
- GTIM3
- GTIM4
- GTIM5
- GTIM6
- GTIM7
- GTIM8
- GTIM9
- GTIM10
param TIM_FiltInitStruct:
- refer to the definition of TIM_FiltInitType
return none
void TIM_IC3FiltConfig(TIM_Module* TIMx, TIM_FiltInitType* TIM_FiltInitStruct)Config the filter of channel3.
Source comment
name TIM_IC3FiltConfig
fun Config the filter of channel3.
param TIMx:
- GTIM1
- GTIM2
- GTIM3
- GTIM4
- GTIM5
- GTIM6
- GTIM7
- GTIM8
- GTIM9
- GTIM10
param TIM_FiltInitStruct:
- refer to the definition of TIM_FiltInitType
return none
void TIM_IC4FiltConfig(TIM_Module* TIMx, TIM_FiltInitType* TIM_FiltInitStruct)Config the filter of channel4.
Source comment
name TIM_IC4FiltConfig
fun Config the filter of channel4.
param TIMx:
- GTIM1
- GTIM2
- GTIM3
- GTIM4
- GTIM5
- GTIM6
- GTIM7
- GTIM8
- GTIM9
- GTIM10
param TIM_FiltInitStruct:
- refer to the definition of TIM_FiltInitType
return none
void TIM_IC1FiltEnable(TIM_Module* TIMx,FunctionalState Cmd)Enable or disable the filter of channel1.
Source comment
name TIM_IC1FiltEnable
fun Enable or disable the filter of channel1.
param TIMx:
- GTIM1
- GTIM2
- GTIM3
- GTIM4
- GTIM5
- GTIM6
- GTIM7
- GTIM8
- GTIM9
- GTIM10
param Cmd :
- ENABLE
- DISABLE
return none
void TIM_IC2FiltEnable(TIM_Module* TIMx,FunctionalState Cmd)Enable or disable the filter of channel2.
Source comment
name TIM_IC2FiltEnable
fun Enable or disable the filter of channel2.
param TIMx:
- GTIM1
- GTIM2
- GTIM3
- GTIM4
- GTIM5
- GTIM6
- GTIM7
- GTIM8
- GTIM9
- GTIM10
param Cmd :
- ENABLE
- DISABLE
return none
void TIM_IC3FiltEnable(TIM_Module* TIMx,FunctionalState Cmd)Enable or disable the filter of channel3.
Source comment
name TIM_IC3FiltEnable
fun Enable or disable the filter of channel3.
param TIMx:
- GTIM1
- GTIM2
- GTIM3
- GTIM4
- GTIM5
- GTIM6
- GTIM7
- GTIM8
- GTIM9
- GTIM10
param Cmd :
- ENABLE
- DISABLE
return none
void TIM_IC4FiltEnable(TIM_Module* TIMx,FunctionalState Cmd)Enable or disable the filter of channel4.
Source comment
name TIM_IC4FiltEnable
fun Enable or disable the filter of channel4.
param TIMx:
- GTIM1
- GTIM2
- GTIM3
- GTIM4
- GTIM5
- GTIM6
- GTIM7
- GTIM8
- GTIM9
- GTIM10
param Cmd :
- ENABLE
- DISABLE
return none
FlagStatus TIM_GetFiltStatus(TIM_Module* TIMx, uint32_t TIM_FiltFlag)Checks the specified filter status.
Source comment
name TIM_GetFiltStatus
fun Checks the specified filter status.
param TIMx (The input parameters must be the following values):
- GTIM1
- GTIM2
- GTIM3
- GTIM4
- GTIM5
- GTIM6
- GTIM7
- GTIM8
- GTIM9
- GTIM10
param TIM_FiltFlag :
- TIM_C1FILTO
- TIM_C2FILTO
- TIM_C3FILTO
- TIM_C4FILTO
return The new state of TIM_FiltFlag (SET or RESET).
5.27.3 Demo descriptions
This section describes the 21 TIM examples: 6Steps outputs a six-step commutation waveform from software commutation events; ATIM1_Synchro, Cascade_Synchro, Parallel_Synchro, and ExtTrigger_Synchro demonstrate timer master/slave synchronization; ComplementarySignals outputs complementary PWM with dead time and a break input; DMA and DMABurst demonstrate update DMA requests and DMA burst transfer; InputCapture and PWM_Input demonstrate input capture and PWM input measurement; OCActive, OCInactive, OCToggle, and OnePulse demonstrate the four output compare modes; PWM_Output outputs four PWM channels with different duty cycles; Quadrature_Output uses a master timer to trigger several outputs with a fixed phase shift; TimeBase toggles four IOs from a compare interrupt; TimeBasic_ATIM1, TimeBasic_BTIM1, TimeBasic_GTIM2, and TimeBasic_GTIM8 demonstrate the update interrupt of the advanced, basic, and general-purpose timers.
5.27.3.1 6Steps six-step commutation
Example directory: projects/n32h49x_EVAL/examples/TIM/6Steps/
Enable the ATIM1 and complementary-channel clocks→Configure the output pins of the three complementary channels→Initialize the ATIM1 time base, compare values, and break settings→Enable the commutation interrupt and the main output→Trigger a software commutation event every 100 ms→Rotate the six commutation states in the interrupt
| Item | Source analysis |
|---|---|
| Function | The three complementary channels of ATIM1 output a six-step commutation waveform: SysTick triggers a software commutation (COM) event every 100 ms, and the commutation interrupt rotates the conduction states of the six channels in the order Step1 to Step6. |
| Source files | src/main.c: clocks, NVIC, GPIO, and SysTick configuration, and the ATIM1 time base, complementary channels, and break configuration;src/n32h49x_it.c: SysTick_Handler generates the commutation events and TIMx_IRQHandler implements the six-step commutation;inc/main.h: the TIMx, six channel-pin, and interrupt-number macros;readme.txt: function, environment, and usage;MDK-ARM/ and EWARM/: Keil and IAR projects. |
| Key configuration | Timer: TIMx is ATIM1, Prescaler 0, Period 4095, CounterMode up, and ClkDiv DIV1;Channels: the compare values of CH1 to CH3 are 2047/1023/511, both OutputState and OutputNState are enabled, and the output polarity is high;Break: OSSR and OSSI enabled, LOCKLevel off, DeadTime 1, Break disabled, and AutomaticOutput enabled;Pins: CH1=PC0, CH2=PA9, CH3=PC2, CH1N=PB13, CH2N=PB14, CH3N=PB1; Interrupt: ATIM1_TRG_COM_IRQn preemption 1 and subpriority 1, and SysTick priority 0; Clock: SysTick 10 ms. |
| Program and data path | main sets up the clocks, interrupts, and six channel pins, configures the ATIM1 time base, compare values, and break settings, and enables the COM interrupt and the main output;SysTick_Handler generates an ATIM1 COM event every ten SysTick interrupts;TIMx_IRQHandler rotates the compare mode and enable state of the three complementary channels per the step state. |
| Main APIs | TIM_InitTimBaseStruct, TIM_InitTimeBase, TIM_InitOc1, TIM_InitOc2, TIM_InitOc3, TIM_InitBkdtStruct, TIM_ConfigBkdt, TIM_ConfigInt, TIM_Enable, TIM_EnableCtrlPwmOutputs, TIM_GenerateEvent, TIM_SelectOcMode, TIM_EnableCapCmpCh |
| Verification | Observe the waveforms of CH1 to CH3 (PC0, PA9, PC2) and the complementary channels (PB13, PB14, PB1) with an oscilloscope or logic analyzer; a commutation event appears every 100 ms, cycling through the six states. |
| Use note | The development environment is KEIL MDK-ARM 5.34 or IAR EWARM 8.50.1; based on the full-function board N32H497ZGL7_EVB V1.0 at HSI+PLL 240 MHz; before use, handle the NSLINK jumper between PA9 and PA10 as described in readme.txt. |
Core-code walkthrough and porting
The example first produces three complementary PWM outputs with fixed settings, then rotates the conduction state of each channel at runtime with software commutation events.
Data path: SysTick_Handler generates a COM event every 100 ms → TIMx_IRQHandler responds and rewrites the channel configuration → the three complementary channels output the new conduction state.
1. The time base and the three complementary channels are initialized with fixed values. The time-base period is 4095, the compare values of CH1 to CH3 are 2047, 1023, and 511, and both the main and complementary outputs of the three channels are enabled.
src/main.csrc/main.c · main
TIM_InitTimBaseStruct(&TIM_TimeBaseStructure);
TIM_TimeBaseStructure.Prescaler = 0;
TIM_TimeBaseStructure.CounterMode = TIM_CNT_MODE_UP;
TIM_TimeBaseStructure.Period = 4095;
TIM_TimeBaseStructure.ClkDiv = TIM_CLK_DIV1;
TIM_TimeBaseStructure.RepetCnt = 0;
TIM_InitTimeBase(TIMx, &TIM_TimeBaseStructure);
/* Channel 1, 2 and 3 Configuration in PWM mode */
TIM_InitOcStruct(&TIM_OCInitStructure);
TIM_OCInitStructure.OCMode = TIM_OCMODE_TIMING;
TIM_OCInitStructure.OutputState = TIM_OUTPUT_STATE_ENABLE;
TIM_OCInitStructure.OutputNState = TIM_OUTPUT_NSTATE_ENABLE;
TIM_OCInitStructure.Pulse = 2047;
TIM_OCInitStructure.OCPolarity = TIM_OC_POLARITY_HIGH;
TIM_OCInitStructure.OCNPolarity = TIM_OCN_POLARITY_HIGH;
TIM_OCInitStructure.OCIdleState = TIM_OC_IDLE_STATE_SET;
TIM_OCInitStructure.OCNIdleState = TIM_OCN_IDLE_STATE_SET;
TIM_InitOc1(TIMx, &TIM_OCInitStructure);
TIM_OCInitStructure.Pulse = 1023;
TIM_InitOc2(TIMx, &TIM_OCInitStructure);
TIM_OCInitStructure.Pulse = 511;
TIM_InitOc3(TIMx, &TIM_OCInitStructure);
2. Enable the commutation interrupt and the main output after the break and dead-time configuration. DeadTime is 1, Break is disabled, and AutomaticOutput is enabled; then the COM interrupt, the counter, and the main output are enabled.
src/main.csrc/main.c · main
/* Automatic Output enable, Break, dead time and lock configuration*/
TIM_InitBkdtStruct(&TIM_BDTRInitStructure);
TIM_BDTRInitStructure.OSSRState = TIM_OSSR_STATE_ENABLE;
TIM_BDTRInitStructure.OSSIState = TIM_OSSI_STATE_ENABLE;
TIM_BDTRInitStructure.LOCKLevel = TIM_LOCK_LEVEL_OFF;
TIM_BDTRInitStructure.DeadTime = 1;
TIM_BDTRInitStructure.Break = TIM_BREAK_IN_DISABLE;
TIM_BDTRInitStructure.AutomaticOutput = TIM_AUTO_OUTPUT_ENABLE;
TIM_ConfigBkdt(TIMx, &TIM_BDTRInitStructure);
TIM_EnableCapCmpPreloadControl(TIMx, ENABLE);
/* interrupt Enable */
TIM_ConfigInt(TIMx, TIM_INT_COM, ENABLE);
/* TIM1 counter enable */
TIM_Enable(TIMx, ENABLE);
/* Main Output Enable */
TIM_EnableCtrlPwmOutputs(TIMx, ENABLE);
3. SysTick generates a commutation event every 100 ms. After ten 10 ms interrupts, software sets a COM event and applies the new preloaded configuration in one go.
src/n32h49x_it.csrc/n32h49x_it.c · SysTick_Handler
void SysTick_Handler(void)
{
if(temp==9)
{
/* Generate TIM1 COM event by software */
TIM_GenerateEvent(TIMx, TIM_EVT_SRC_COM);
temp=0;
}
else
{
temp++;
}
}
4. The commutation interrupt rotates the channels by state. Each COM interrupt rewrites the output compare mode and the main/complementary enables of the three channels according to step, producing the six-state cycle.
src/n32h49x_it.csrc/n32h49x_it.c · TIMx_IRQHandler
/* Clear TIMx COM pending bit */
TIM_ClrIntPendingBit(TIMx, TIM_INT_COM);
if (step == 1)
{
/* Next step: Step 2 Configuration ---------------------------- */
/* Channel3 configuration */
TIM_EnableCapCmpCh(TIMx, TIM_CH_3, TIM_CAP_CMP_DISABLE);
TIM_EnableCapCmpChN(TIMx, TIM_CH_3, TIM_CAP_CMP_N_DISABLE);
/* Channel1 configuration */
TIM_SelectOcMode(TIMx, TIM_CH_1, TIM_OCMODE_PWM1);
TIM_EnableCapCmpCh(TIMx, TIM_CH_1, TIM_CAP_CMP_ENABLE);
TIM_EnableCapCmpChN(TIMx, TIM_CH_1, TIM_CAP_CMP_N_DISABLE);
/* Channel2 configuration */
TIM_SelectOcMode(TIMx, TIM_CH_2, TIM_OCMODE_PWM1);
TIM_EnableCapCmpCh(TIMx, TIM_CH_2, TIM_CAP_CMP_DISABLE);
TIM_EnableCapCmpChN(TIMx, TIM_CH_2, TIM_CAP_CMP_N_ENABLE);
step++;
}
Corresponding source files: src/main.c, src/n32h49x_it.c
5.27.3.2 ATIM1_Synchro gated synchronization from ATIM1
Example directory: projects/n32h49x_EVAL/examples/TIM/ATIM1_Synchro/
Enable the ATIM1, GTIM3, and GTIM4 clocks→Configure the three CH1 alternate-function output pins→Initialize ATIM1 as a PWM master timer and select the update event as the trigger output→Configure GTIM3 and GTIM4 as gated slave timers selecting ITR0→Enable the three timers and turn on the ATIM1 main output
| Item | Source analysis |
|---|---|
| Function | ATIM1 acts as the master timer and outputs PWM, and its update event gates GTIM3 and GTIM4 through the trigger output; the two slave timers count and output PWM within each ATIM1 period, with periods about 15 and 10 times that of ATIM1. |
| Source files | src/main.c: clock and GPIO configuration, and the time base, PWM, and master/slave mode configuration of ATIM1, GTIM3, and GTIM4;inc/main.h: standard header includes and function declarations;src/n32h49x_it.c and inc/n32h49x_it.h: interrupt handlers;readme.txt: function, environment, and usage;MDK-ARM/ and EWARM/: Keil and IAR projects. |
| Key configuration | Master timer: ATIM1 Period 255, RepetCnt 4, Pulse 127, OCMODE_PWM2, and trigger output on the update event;Slave timers: GTIM3 Period 2 and GTIM4 Period 1, both in gated slave mode with trigger input ITR0;Pins: ATIM1 CH1=PA8, GTIM3 CH1=PA11, GTIM4 CH1=PA0, all alternate push-pull outputs; Clock: RCC_ConfigPclk1(RCC_HCLK_DIV4);Mode: ATIM1 master/slave mode enabled. |
| Program and data path | main first configures the gated slave mode and time base of GTIM3 and GTIM4, then the time base, PWM channel, and master mode of ATIM1;TIM_SelectOutputTrig makes ATIM1 output a trigger on each update event as the gated input of the two slave timers;ATIM1, GTIM3, and GTIM4 are enabled in turn and the ATIM1 main output is turned on, and the slave timers count within the gated window and output PWM. |
| Main APIs | TIM_InitTimBaseStruct, TIM_InitTimeBase, TIM_InitOcStruct, TIM_InitOc1, TIM_SelectSlaveMode, TIM_SelectInputTrig, TIM_SelectOutputTrig, TIM_SelectMasterSlaveMode, TIM_Enable, TIM_EnableCtrlPwmOutputs |
| Verification | Observe ATIM1 CH1 (PA8), GTIM3 CH1 (PA11), and GTIM4 CH1 (PA0) at the same time with an oscilloscope or logic analyzer; the output periods of the two slave timers are about 15 and 10 times that of ATIM1. |
| Use note | The development environment is KEIL MDK-ARM 5.34 or IAR EWARM 8.50.1; based on the full-function board N32H497ZGL7_EVB V1.0 at HSI+PLL 240 MHz; RCC_ConfigPclk1(RCC_HCLK_DIV4) is used because the maximum operating clock of GTIM1 to GTIM7 and BTIM1 to BTIM2 is 120 MHz, so the PCLK1 division must not be 1 or 2. |
Core-code walkthrough and porting
The example configures ATIM1 as a master timer and GTIM3 and GTIM4 as gated slave timers; reading the configuration points below along the master/slave trigger chain explains the gating relationship.
Data path: ATIM1 update event → ATIM1 trigger output → GTIM3 and GTIM4 gated inputs (ITR0) → the slave counters count within the gated window → CH1 outputs PWM.
1. The slave timers receive the master trigger in gated slave mode. The trigger input of GTIM3 and GTIM4 selects ITR0, and counting start and stop are controlled by the ATIM1 trigger output.
src/main.csrc/main.c · main
TIM_InitTimBaseStruct(&TIM_TimeBaseStructure);
TIM_TimeBaseStructure.Period = 2;
TIM_TimeBaseStructure.Prescaler = 0;
TIM_TimeBaseStructure.ClkDiv = TIM_CLK_DIV1;
TIM_TimeBaseStructure.CounterMode = TIM_CNT_MODE_UP;
TIM_InitTimeBase(GTIM3, &TIM_TimeBaseStructure);
TIM_InitOcStruct(&TIM_OCInitStructure);
TIM_OCInitStructure.OCMode = TIM_OCMODE_PWM1;
TIM_OCInitStructure.OutputState = TIM_OUTPUT_STATE_ENABLE;
TIM_OCInitStructure.Pulse = 1;
TIM_InitOc1(GTIM3, &TIM_OCInitStructure);
/* Slave Mode selection: GTIM3 */
TIM_SelectSlaveMode(GTIM3, TIM_SLAVE_MODE_GATED);
TIM_SelectInputTrig(GTIM3, TIM_TRIG_SEL_IN_TR0);
2. The master timer uses the update event as the trigger output. ATIM1 is configured as PWM2 and the update event is selected as the trigger output, sending one gating signal to the slave timers in each counting period.
src/main.csrc/main.c · main
/* Time Base configuration */
TIM_TimeBaseStructure.Prescaler = 0;
TIM_TimeBaseStructure.CounterMode = TIM_CNT_MODE_UP;
TIM_TimeBaseStructure.Period = 255;
TIM_TimeBaseStructure.ClkDiv = TIM_CLK_DIV1;
TIM_TimeBaseStructure.RepetCnt = 4;
TIM_InitTimeBase(ATIM1, &TIM_TimeBaseStructure);
/* Channel 1 Configuration in PWM mode */
TIM_OCInitStructure.OCMode = TIM_OCMODE_PWM2;
TIM_OCInitStructure.OutputState = TIM_OUTPUT_STATE_ENABLE;
TIM_OCInitStructure.OutputNState = TIM_OUTPUT_NSTATE_ENABLE;
TIM_OCInitStructure.Pulse = 127;
TIM_OCInitStructure.OCPolarity = TIM_OC_POLARITY_LOW;
TIM_OCInitStructure.OCNPolarity = TIM_OCN_POLARITY_LOW;
TIM_OCInitStructure.OCIdleState = TIM_OC_IDLE_STATE_SET;
TIM_OCInitStructure.OCNIdleState = TIM_OCN_IDLE_STATE_RESET;
TIM_InitOc1(ATIM1, &TIM_OCInitStructure);
/* Master Mode selection */
TIM_SelectOutputTrig(ATIM1, TIM_TRGO_SRC_UPDATE);
/* Select the Master Slave Mode */
TIM_SelectMasterSlaveMode(ATIM1, TIM_MASTER_SLAVE_MODE_ENABLE);
3. The three output pins are all alternate push-pull. CH1 of ATIM1 uses AF3, and CH1 of GTIM3 and GTIM4 uses AF2.
src/main.csrc/main.c · GPIO_Configuration
GPIO_InitStruct(&GPIO_InitStructure);
/* GPIOx Configuration: Pin of TIMx */
GPIO_InitStructure.Pin = GPIO_PIN_8;
GPIO_InitStructure.GPIO_Mode = GPIO_MODE_AF_PP;
GPIO_InitStructure.GPIO_Slew_Rate = GPIO_SLEW_RATE_SLOW;
GPIO_InitStructure.GPIO_Alternate = GPIO_AF3;
GPIO_InitPeripheral(GPIOA, &GPIO_InitStructure);
/* GPIOx Configuration: Pin of TIMx */
GPIO_InitStructure.Pin = GPIO_PIN_11 | GPIO_PIN_0;
GPIO_InitStructure.GPIO_Mode = GPIO_MODE_AF_PP;
GPIO_InitStructure.GPIO_Slew_Rate = GPIO_SLEW_RATE_SLOW;
GPIO_InitStructure.GPIO_Alternate = GPIO_AF2;
GPIO_InitPeripheral(GPIOA, &GPIO_InitStructure);
4. PCLK1 division and timer clock enable. The maximum operating clock of the general-purpose timers is 120 MHz, so PCLK1 must be divided by 4 before the timer clocks are enabled.
src/main.csrc/main.c · RCC_Configuration
/* TIMx, GPIOx and AFIO clocks enable */
RCC_ConfigPclk1(RCC_HCLK_DIV4);/* The maximum operating clock of GTIM1-7/BTIM1-2 is 120MHz,the division frequency of PCLK1 cannot be 1 or 2 divisions */
RCC_EnableAHBPeriphClk(RCC_AHB_PERIPHEN_ATIM1,ENABLE);
RCC_EnableAPB1PeriphClk(RCC_APB1_PERIPHEN_GTIM3 | RCC_APB1_PERIPHEN_GTIM4,ENABLE);
RCC_EnableAHB1PeriphClk(RCC_AHB_PERIPHEN_GPIOA,ENABLE);
RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPHEN_AFIO,ENABLE);
Corresponding source files: src/main.c
5.27.3.3 Cascade_Synchro cascade synchronization
Example directory: projects/n32h49x_EVAL/examples/TIM/Cascade_Synchro/
Enable the TIMx, TIMy, and TIMz clocks→Configure the three CH1 alternate-function output pins→TIMx acts as a PWM master timer with the update event as the trigger output→TIMy is gated by TIMx and acts as a master timer itself→TIMz is gated by TIMy, forming a two-stage cascade→Enable the three timers in turn and observe the three outputs
| Item | Source analysis |
|---|---|
| Function | GTIM2 acts as the master timer and outputs PWM, and its update event gates GTIM5; GTIM5 in turn gates GTIM6 with its own update event, so the three timers cascade and the period of each stage becomes 4 times that of the previous one. |
| Source files | src/main.c: clock and GPIO configuration, and the time base, PWM, and master/slave mode configuration of TIMx, TIMy, and TIMz;inc/main.h: TIMx is GTIM2, TIMy is GTIM5, TIMz is GTIM6, and the pin macros of each channel;src/n32h49x_it.c and inc/n32h49x_it.h: interrupt handlers;readme.txt: function, environment, and usage;MDK-ARM/ and EWARM/: Keil and IAR projects. |
| Key configuration | Timers: TIMx Period 255 and TIMy and TIMz Period 3, Prescaler 0, and ClkDiv DIV1;Channels: the three CH1 channels are all OCMODE_PWM1, TIMx Pulse 64 and TIMy and TIMz Pulse 1;Slave mode: TIMy trigger input ITR2 and TIMz trigger input ITR12, both in gated slave mode; Mode: both TIMx and TIMy enable master/slave mode and use the update event as the trigger output; Pins: GTIM2 CH1=PA6, GTIM5 CH1=PA2, GTIM6 CH1=PD5. |
| Program and data path | main sets the time base of the three timers in turn, with TIMx period 255 and TIMy and TIMz period 3;then TIMx and TIMy are both set to master/slave mode with the update event as the trigger output, and TIMy and TIMz receive the trigger of the previous stage in gated slave mode; after TIMy, TIMx, and TIMz are enabled in turn, the trigger edge propagates down stage by stage and the period of each of the three outputs becomes 4 times that of the previous one. |
| Main APIs | TIM_InitTimBaseStruct, TIM_InitTimeBase, TIM_InitOcStruct, TIM_InitOc1, TIM_SelectMasterSlaveMode, TIM_SelectOutputTrig, TIM_SelectSlaveMode, TIM_SelectInputTrig, TIM_Enable |
| Verification | Observe GTIM2 CH1 (PA6), GTIM5 CH1 (PA2), and GTIM6 CH1 (PD5) at the same time with an oscilloscope or logic analyzer; the GTIM5 period is 4 times that of GTIM2 and the GTIM6 period is 4 times that of GTIM5. |
| Use note | The development environment is KEIL MDK-ARM 5.34 or IAR EWARM 8.50.1; based on the full-function board N32H497ZGL7_EVB V1.0 at HSI+PLL 240 MHz; RCC_ConfigPclk1(RCC_HCLK_DIV4) is used because the maximum operating clock of GTIM1 to GTIM7 and BTIM1 to BTIM2 is 120 MHz. |
Core-code walkthrough and porting
The example chains three general-purpose timers stage by stage, and each stage uses its update event to trigger the gated input of the next stage.
Data path: TIMx update event → TIMy gated input (ITR2) → TIMy update event → TIMz gated input (ITR12) → the three CH1 channels output PWM.
1. Time base and PWM compare values of the three stages. TIMx period 255 and TIMy and TIMz period 3, and the three CH1 channels are all configured as PWM1.
src/main.csrc/main.c · main
/* Time Base configuration */
TIM_InitTimBaseStruct(&TIM_TimeBaseStructure);
TIM_TimeBaseStructure.Prescaler = 0;
TIM_TimeBaseStructure.CounterMode = TIM_CNT_MODE_UP;
TIM_TimeBaseStructure.Period = 255;
TIM_TimeBaseStructure.ClkDiv = TIM_CLK_DIV1;
TIM_InitTimeBase(TIMx, &TIM_TimeBaseStructure);
TIM_TimeBaseStructure.Period = 3;
TIM_InitTimeBase(TIMy, &TIM_TimeBaseStructure);
TIM_TimeBaseStructure.Period = 3;
TIM_InitTimeBase(TIMz, &TIM_TimeBaseStructure);
2. TIMx acts as the master timer and outputs the trigger. TIMx enables master/slave mode and selects the update event as the trigger output.
src/main.csrc/main.c · main
/* Master Configuration in PWM1 Mode */
TIM_InitOcStruct(&TIM_OCInitStructure);
TIM_OCInitStructure.OCMode = TIM_OCMODE_PWM1;
TIM_OCInitStructure.OutputState = TIM_OUTPUT_STATE_ENABLE;
TIM_OCInitStructure.Pulse = 64;
TIM_OCInitStructure.OCPolarity = TIM_OC_POLARITY_HIGH;
TIM_InitOc1(TIMx, &TIM_OCInitStructure);
/* Select the Master Slave Mode */
TIM_SelectMasterSlaveMode(TIMx, TIM_MASTER_SLAVE_MODE_ENABLE);
/* Master Mode selection */
TIM_SelectOutputTrig(TIMx, TIM_TRGO_SRC_UPDATE);
3. TIMy is both a slave timer and a master timer. TIMy is gated by ITR2 and at the same time uses its own update event as the trigger output to gate TIMz.
src/main.csrc/main.c · main
/* Slave Mode selection: TIMy */
TIM_SelectSlaveMode(TIMy, TIM_SLAVE_MODE_GATED);
TIM_SelectInputTrig(TIMy, TIM_TRIG_SEL_IN_TR2);
/* Select the Master Slave Mode */
TIM_SelectMasterSlaveMode(TIMy, TIM_MASTER_SLAVE_MODE_ENABLE);
/* Master Mode selection: TIMy */
TIM_SelectOutputTrig(TIMy, TIM_TRGO_SRC_UPDATE);
/* Slave Mode selection: TIMz */
TIM_SelectSlaveMode(TIMz, TIM_SLAVE_MODE_GATED);
TIM_SelectInputTrig(TIMz, TIM_TRIG_SEL_IN_TR12);
4. Clock configuration and division limit. The three timers are all on APB1, and PCLK1 must be divided by 4 so as not to exceed 120 MHz.
src/main.csrc/main.c · RCC_Configuration
/* TIMx, GPIOx and AFIO clocks enable */
RCC_ConfigPclk1(RCC_HCLK_DIV4);/* The maximum operating clock of GTIM1-7/BTIM1-2 is 120MHz,the division frequency of PCLK1 cannot be 1 or 2 divisions */
RCC_EnableAPB1PeriphClk(TIMx_CLK | TIMy_CLK | TIMz_CLK,ENABLE);
RCC_EnableAHB1PeriphClk(TIMx_CH1_GPIO_CLK | TIMy_CH1_GPIO_CLK | TIMz_CH1_GPIO_CLK,ENABLE);
RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPHEN_AFIO,ENABLE);
Corresponding source files: src/main.c
5.27.3.4 ComplementarySignals complementary signal output
Example directory: projects/n32h49x_EVAL/examples/TIM/ComplementarySignals/
Enable the ATIM1 and channel clocks→Configure the four complementary channels and the BKIN pin→Compute the period and the four compare values from the system clock→Initialize the ATIM1 time base and the four PWM channels→Configure the dead time, break, and automatic output enable→Enable the counter and the main output
| Item | Source analysis |
|---|---|
| Function | The four complementary channels of ATIM1 output PWM with fixed duty cycles: CH1 is 50%, CH2 is 25%, and CH3 and CH4 are 12.5%; dead time is inserted, the break input is enabled, and automatic output is configured, for driving complementary bridge arms. |
| Source files | src/main.c: clock and GPIO configuration, and the time base, four complementary PWM channels, and break/dead-time configuration of ATIM1;inc/main.h: TIMx is ATIM1, and the pin macros of the four channels, the complementary channels, and BKIN;src/n32h49x_it.c and inc/n32h49x_it.h: interrupt handlers;readme.txt: function, environment, and usage;MDK-ARM/ and EWARM/: Keil and IAR projects. |
| Key configuration | Timer: TIMx is ATIM1, Prescaler 0, Period derived from SystemCoreClock/16000-1, and ClkDiv DIV1;Channels: CH1 to CH4 are all OCMODE_PWM2, OutputState and OutputNState are enabled, and the output polarity and idle states are set in pairs;Break: DeadTime 11, Break enabled, BreakPolarity active high, and AutomaticOutput enabled;Pins: CH1=PC0, CH2=PA9, CH3=PC2, CH4=PC3, CH1N=PA7, CH2N=PB14, CH3N=PD9, CH4N=PD5, BKIN=PA6; Input: TIM_BreakInputSourceEnable enables the BKIN break input source. |
| Program and data path | main first computes the period and the four compare values from SystemCoreClock, then configures the ATIM1 time base and the four complementary PWM channels;next it configures the break, dead time, and automatic output, and enables the BKIN input source; finally it enables the counter and the main output in turn, and the four complementary channels start to output. |
| Main APIs | TIM_InitTimBaseStruct, TIM_InitTimeBase, TIM_InitOcStruct, TIM_InitOc1, TIM_InitOc2, TIM_InitOc3, TIM_InitOc4, TIM_InitBkdtStruct, TIM_ConfigBkdt, TIM_BreakInputSourceEnable, TIM_Enable, TIM_EnableCtrlPwmOutputs |
| Verification | Observe the waveforms and dead time of the four complementary channels (PC0/PA7, PA9/PB14, PC2/PD9, PC3/PD5) with an oscilloscope; pulling BKIN (PA6) to the active level triggers a break, and the outputs are forced to the idle state. |
| Use note | The development environment is KEIL MDK-ARM 5.34 or IAR EWARM 8.50.1; based on the full-function board N32H497ZGL7_EVB V1.0 at HSI+PLL 240 MHz; handle the NSLINK jumper between PA9 and PA10 as described in readme.txt so that the debug link does not affect the channel outputs. |
Core-code walkthrough and porting
The example uses ATIM1 to produce four pairs of complementary PWM outputs and demonstrates the complementary output path of the advanced timer with the break and dead-time configuration.
Data path: SystemCoreClock → period and compare value computation → ATIM1 time base and four PWM channels → dead time and break configuration → the four complementary channels output.
1. The period and duty cycles are computed from the system clock. The period is SystemCoreClock/16000-1, and the four compare values are computed for 50%, 25%, 12.5%, and 12.5%.
src/main.csrc/main.c · main
/* Compute the value to be set in AR register to generate signal frequency at x hz */
TimerPeriod = (SystemCoreClock / 16000) - 1;
/* Compute CCDAT1 value to generate a duty cycle at 50% for channel 1 */
Channel1Pulse = (uint16_t)(((uint32_t)5 * (TimerPeriod - 1)) / 10);
/* Compute CCDAT2 value to generate a duty cycle at 25% for channel 2 */
Channel2Pulse = (uint16_t)(((uint32_t)25 * (TimerPeriod - 1)) / 100);
/* Compute CCDAT3 value to generate a duty cycle at 12.5% for channel 3 */
Channel3Pulse = (uint16_t)(((uint32_t)125 * (TimerPeriod - 1)) / 1000);
/* Compute CCDAT4 value to generate a duty cycle at 12.5% for channel 3 */
Channel4Pulse = (uint16_t)(((uint32_t)125 * (TimerPeriod - 1)) / 1000);
2. The four complementary channels output in PWM2. The main and complementary outputs are enabled, and the output polarity and idle states are set in pairs.
src/main.csrc/main.c · main
/* Time Base configuration */
TIM_InitTimBaseStruct(&TIM_TimeBaseStructure);
TIM_TimeBaseStructure.Prescaler = 0;
TIM_TimeBaseStructure.CounterMode = TIM_CNT_MODE_UP;
TIM_TimeBaseStructure.Period = TimerPeriod;
TIM_TimeBaseStructure.ClkDiv = TIM_CLK_DIV1;
TIM_TimeBaseStructure.RepetCnt = 0;
TIM_InitTimeBase(TIMx, &TIM_TimeBaseStructure);
/* Channel 1, 2 and 3 Configuration in PWM mode */
TIM_InitOcStruct(&TIM_OCInitStructure);
TIM_OCInitStructure.OCMode = TIM_OCMODE_PWM2;
TIM_OCInitStructure.OutputState = TIM_OUTPUT_STATE_ENABLE;
TIM_OCInitStructure.OutputNState = TIM_OUTPUT_NSTATE_ENABLE;
TIM_OCInitStructure.Pulse = Channel1Pulse;
TIM_OCInitStructure.OCPolarity = TIM_OC_POLARITY_LOW;
TIM_OCInitStructure.OCNPolarity = TIM_OCN_POLARITY_LOW;
TIM_OCInitStructure.OCIdleState = TIM_OC_IDLE_STATE_SET;
TIM_OCInitStructure.OCNIdleState = TIM_OCN_IDLE_STATE_RESET;
TIM_InitOc1(TIMx, &TIM_OCInitStructure);
TIM_OCInitStructure.Pulse = Channel2Pulse;
TIM_InitOc2(TIMx, &TIM_OCInitStructure);
TIM_OCInitStructure.Pulse = Channel3Pulse;
TIM_InitOc3(TIMx, &TIM_OCInitStructure);
TIM_OCInitStructure.Pulse = Channel4Pulse;
TIM_InitOc4(TIMx, &TIM_OCInitStructure);
3. Dead time, break, and automatic output enable. DeadTime is 11, the break is active high and automatic output is enabled, and the BKIN input source is enabled separately.
src/main.csrc/main.c · main
/* Automatic Output enable, Break, dead time and lock configuration*/
TIM_InitBkdtStruct(&TIM_BDTRInitStructure);
TIM_BDTRInitStructure.OSSRState = TIM_OSSR_STATE_ENABLE;
TIM_BDTRInitStructure.OSSIState = TIM_OSSI_STATE_ENABLE;
TIM_BDTRInitStructure.LOCKLevel = TIM_LOCK_LEVEL_OFF;
TIM_BDTRInitStructure.DeadTime = 11;
TIM_BDTRInitStructure.Break = TIM_BREAK_IN_ENABLE;
TIM_BDTRInitStructure.BreakPolarity = TIM_BREAK_POLARITY_HIGH;
TIM_BDTRInitStructure.AutomaticOutput = TIM_AUTO_OUTPUT_ENABLE;
TIM_ConfigBkdt(TIMx, &TIM_BDTRInitStructure);
TIM_BreakInputSourceEnable(TIMx,TIM_BREAK_IOM,TIM_BREAK_SOURCE_POLARITY_NONINVERT,ENABLE);
/* TIMx counter enable */
TIM_Enable(TIMx, ENABLE);
/* Main Output Enable */
TIM_EnableCtrlPwmOutputs(TIMx, ENABLE);
Corresponding source files: src/main.c
5.27.3.5 DMA update-event-triggered DMA transfer
Example directory: projects/n32h49x_EVAL/examples/TIM/DMA/
Enable the ATIM1, GPIO, and DMA1 clocks→Configure the CH3 and CH3N alternate-function output pins→Compute the period and three duty cycles→Initialize the ATIM1 time base and the CH3 complementary PWM→Configure DMA1_CH5 and remap it to the update request→Enable the update DMA request, the counter, and the main output
| Item | Source analysis |
|---|---|
| Function | ATIM1 CH3 outputs complementary PWM whose duty cycle is rewritten cyclically by DMA; at the pace set by the repetition counter, the compare value cycles between 50%, 37.5%, and 25%. |
| Source files | src/main.c: clock and GPIO configuration, and the ATIM1 time base, CH3 complementary PWM, update DMA request, and DMA channel configuration;inc/main.h: TIMx is ATIM1, the CH3 and CH3N pin macros, and the SRC_Buffer declaration;src/n32h49x_it.c and inc/n32h49x_it.h: interrupt handlers;readme.txt: function, environment, and usage;MDK-ARM/ and EWARM/: Keil and IAR projects. |
| Key configuration | Timer: TIMx is ATIM1, Prescaler 0, Period derived from SystemCoreClock/60000-1, and RepetCnt 5;Channel: CH3 uses OCMODE_PWM2, OutputState and OutputNState are enabled, and Pulse is SRC_Buffer[0];DMA: DMA1 channel 5, peripheral address TIMx->CCDAT3, memory address SRC_Buffer, BufSize 3, circular mode, and word-wide transfer;Request: the ATIM1 update DMA request is enabled and remapped to DMA1_CH5; Pins: CH3=PC2, CH3N=PD9. |
| Program and data path | main first computes the period and three duty cycles into SRC_Buffer, then configures the ATIM1 time base and the CH3 complementary PWM and turns on the update DMA request;DMA_Configuration configures DMA1_CH5 to copy cyclically from SRC_Buffer to CCDAT3;each update event triggers one DMA request and the compare value switches to the next level. |
| Main APIs | TIM_InitTimBaseStruct, TIM_InitTimeBase, TIM_InitOcStruct, TIM_InitOc3, TIM_EnableDma, TIM_Enable, TIM_EnableCtrlPwmOutputs, DMA_Init, DMA_StructInit, DMA_DeInit, DMA_RequestRemap, DMA_EnableChannel |
| Verification | Observe the complementary PWM of CH3/CH3N (PC2, PD9) with an oscilloscope; the duty cycle cycles among 50%, 37.5%, and 25% at the pace of the repetition counter. |
| Use note | The development environment is KEIL MDK-ARM 5.34 or IAR EWARM 8.50.1; based on the full-function board N32H497ZGL7_EVB V1.0 at HSI+PLL 240 MHz; the DMA channel and request mapping must follow the device request table, and the remap must be changed together when the timer or channel changes. |
Core-code walkthrough and porting
The example uses the update DMA request to feed the compare values in a one-dimensional array into ATIM1 CH3 cyclically, switching the duty cycle automatically.
Data path: SRC_Buffer → DMA1_CH5 (circular, word-wide) → TIMx->CCDAT3 → CH3 and CH3N complementary output.
1. The period and three duty cycles are computed in one go. The period is SystemCoreClock/60000-1, and the three duty cycles are stored in SRC_Buffer.
src/main.csrc/main.c · main
/* Compute the value to be set in AR register to generate signal frequency at x hz */
TimerPeriod = (SystemCoreClock / 60000) - 1;
/* Compute CCDAT1 value to generate a duty cycle at 50% */
SRC_Buffer[0] = (uint16_t)(((uint32_t)5 * (TimerPeriod - 1)) / 10);
/* Compute CCDAT1 value to generate a duty cycle at 37.5% */
SRC_Buffer[1] = (uint16_t)(((uint32_t)375 * (TimerPeriod - 1)) / 1000);
/* Compute CCDAT1 value to generate a duty cycle at 25% */
SRC_Buffer[2] = (uint16_t)(((uint32_t)25 * (TimerPeriod - 1)) / 100);
2. The update DMA request is enabled and the CH3 output configured. ATIM1 turns on the update DMA request, and CH3 uses SRC_Buffer[0] as the compare value in PWM2 mode.
src/main.csrc/main.c · main
/* Time Base configuration */
TIM_InitTimBaseStruct(&TIM_TimeBaseStructure);
TIM_TimeBaseStructure.Prescaler = 0;
TIM_TimeBaseStructure.CounterMode = TIM_CNT_MODE_UP;
TIM_TimeBaseStructure.Period = TimerPeriod;
TIM_TimeBaseStructure.ClkDiv = TIM_CLK_DIV1;
TIM_TimeBaseStructure.RepetCnt = 5;
TIM_InitTimeBase(TIMx, &TIM_TimeBaseStructure);
/* Channel 3 Configuration in PWM mode */
TIM_InitOcStruct(&TIM_OCInitStructure);
TIM_OCInitStructure.OCMode = TIM_OCMODE_PWM2;
TIM_OCInitStructure.OutputState = TIM_OUTPUT_STATE_ENABLE;
TIM_OCInitStructure.OutputNState = TIM_OUTPUT_NSTATE_ENABLE;
TIM_OCInitStructure.Pulse = SRC_Buffer[0];
TIM_OCInitStructure.OCPolarity = TIM_OC_POLARITY_LOW;
TIM_OCInitStructure.OCNPolarity = TIM_OCN_POLARITY_LOW;
TIM_OCInitStructure.OCIdleState = TIM_OC_IDLE_STATE_SET;
TIM_OCInitStructure.OCNIdleState = TIM_OCN_IDLE_STATE_RESET;
TIM_InitOc3(TIMx, &TIM_OCInitStructure);
/* TIMx Update DMA Request enable */
TIM_EnableDma(TIMx, TIM_DMA_UPDATE, ENABLE);
/* TIMx counter enable */
TIM_Enable(TIMx, ENABLE);
3. The DMA channel copies the compare values cyclically. DMA1_CH5 uses the peripheral as the destination and SRC_Buffer as the source, transfers word by word in circular mode, and is remapped to the update request.
src/main.csrc/main.c · DMA_Configuration
/* DMA1 Channel5 Config */
DMA_DeInit(DMA1_CH5);
DMA_StructInit(&DMA_InitStructure);
DMA_InitStructure.PeriphAddr = (uint32_t)&TIMx->CCDAT3;
DMA_InitStructure.MemAddr = (uint32_t)SRC_Buffer;
DMA_InitStructure.Direction = DMA_DIR_PERIPH_DST;
DMA_InitStructure.BufSize = 3;
DMA_InitStructure.PeriphInc = DMA_PERIPH_INC_DISABLE;
DMA_InitStructure.MemoryInc = DMA_MEM_INC_ENABLE;
DMA_InitStructure.PeriphDataSize = DMA_PERIPH_DATA_WIDTH_WORD;
DMA_InitStructure.MemDataSize = DMA_MEM_DATA_WIDTH_WORD;
DMA_InitStructure.CircularMode = DMA_MODE_CIRCULAR;
DMA_InitStructure.Priority = DMA_PRIORITY_HIGH;
DMA_InitStructure.Mem2Mem = DMA_M2M_DISABLE;
DMA_Init(DMA1_CH5, &DMA_InitStructure);
DMA_RequestRemap(DMA_REMAP_ATIM1_UP,DMA1_CH5, ENABLE);
/* DMA1 Channel5 enable */
DMA_EnableChannel(DMA1_CH5, ENABLE);
Corresponding source files: src/main.c
5.27.3.6 DMABurst DMA burst transfer
Example directory: projects/n32h49x_EVAL/examples/TIM/DMABurst/
Enable the ATIM1, GPIO, and DMA1 clocks→Configure the CH1 alternate-function output pin→Initialize the ATIM1 time base and CH1 PWM→Configure the DMA burst base address and transfer length→Configure and start DMA1_CH5 to transfer 8 words→Poll the completion flag and repeat the burst in a loop
| Item | Source analysis |
|---|---|
| Function | ATIM1 CH1 outputs PWM, and the compare value is written in one DMA burst of 8 transfers;SRC_Buffer specifies the start and end positions of the pulse within the period, and after the transfer completes the background loop triggers it again. |
| Source files | src/main.c: clock and GPIO configuration, and the ATIM1 time base, CH1 PWM, DMA burst setting, and channel configuration;inc/main.h: TIMx is ATIM1, the CH1 pin macro, and the SRC_Buffer declaration;src/n32h49x_it.c and inc/n32h49x_it.h: interrupt handlers;readme.txt: function, environment, and usage;MDK-ARM/ and EWARM/: Keil and IAR projects. |
| Key configuration | Timer: TIMx is ATIM1, Prescaler 0, Period 0xFFFF, and ClkDiv DIV1;Channel: CH1 uses OCMODE_PWM1, Pulse 0x8FFF, and OutputState enabled;Burst: TIM_ConfigDma sets the base address to capture/compare data 1 and the burst length to 8 transfers, and enables the update DMA request;DMA: DMA1_CH5, peripheral address TIMx->DADDR, BufSize 8, normal mode, and word-wide transfer;Pin: CH1=PC0. |
| Program and data path | main configures the time base, CH1 PWM, and the DMA burst base address and length, enables the update DMA request, and then starts DMA1_CH5;the 8 words of SRC_Buffer are written to the burst buffer at once, and the background loop repeats the whole process when DmaAgain is set;the program polls the TC5 flag with DMA_GetFlagStatus to wait for the end of transfer, then clears the flags ready for the next time. |
| Main APIs | TIM_InitTimBaseStruct, TIM_InitTimeBase, TIM_InitOcStruct, TIM_InitOc1, TIM_ConfigDma, TIM_EnableDma, TIM_Enable, TIM_EnableCtrlPwmOutputs, DMA_Init, DMA_DeInit, DMA_RequestRemap, DMA_EnableChannel, DMA_GetFlagStatus, DMA_ClearFlag |
| Verification | Observe the PWM of CH1 (PC0) with an oscilloscope; after the burst write the pulse position is set at once according to SRC_Buffer, and once the transfer completion flag TC5 is set the loop triggers it again. |
| Use note | The development environment is KEIL MDK-ARM 5.34 or IAR EWARM 8.50.1; based on the full-function board N32H497ZGL7_EVB V1.0 at HSI+PLL 240 MHz; the burst length must match the DMA buffer size, and the base address must point to the corresponding capture/compare data register. |
Core-code walkthrough and porting
The example writes 8 compare and capture data at once with a single DMA burst into ATIM1, describing the start and end positions of a pulse.
Data path: SRC_Buffer[8] → DMA1_CH5 (normal mode, word-wide) → TIMx->DADDR burst buffer → CH1 outputs the corresponding pulse.
1. The time base, CH1, and the burst base address are configured in one go. The period is 0xFFFF, the CH1 compare value is 0x8FFF, the burst base address is capture/compare data 1, and the length is 8 transfers.
src/main.csrc/main.c · main
TIM_InitTimBaseStruct(&TIM_TimeBaseStructure);
TIM_TimeBaseStructure.Period = 0xFFFF;
TIM_TimeBaseStructure.Prescaler = 0;
TIM_TimeBaseStructure.ClkDiv = TIM_CLK_DIV1;
TIM_TimeBaseStructure.CounterMode = TIM_CNT_MODE_UP;
TIM_InitTimeBase(TIMx, &TIM_TimeBaseStructure);
/* TIM Configuration in PWM Mode */
TIM_InitOcStruct(&TIM_OCInitStructure);
TIM_OCInitStructure.OCMode = TIM_OCMODE_PWM1;
TIM_OCInitStructure.OutputState = TIM_OUTPUT_STATE_ENABLE;
TIM_OCInitStructure.Pulse = 0x8FFF;
TIM_InitOc1(TIMx, &TIM_OCInitStructure);
/* TIMx DADDR Base register and DMA Burst Length Config */
TIM_ConfigDma(TIMx, TIM_DMABASE_CAPCMPDAT1, TIM_DMABURST_LENGTH_8TRANSFERS);
/* TIMx DMA Update enable */
TIM_EnableDma(TIMx, TIM_DMA_UPDATE, ENABLE);
/* TIMx enable */
TIM_Enable(TIMx, ENABLE);
2. The DMA channel transfers 8 words in normal mode. The peripheral address is TIMx->DADDR, the buffer size is 8, memory is incremented, the transfer is word-wide, and it is remapped to the update request.
src/main.csrc/main.c · DMA_Configuration
/* DMA Channel5 Config */
DMA_DeInit(DMA1_CH5);
DMA_StructInit(&DMA_InitStructure);
DMA_InitStructure.PeriphAddr = (uint32_t)&TIMx->DADDR;
DMA_InitStructure.MemAddr = (uint32_t)SRC_Buffer;
DMA_InitStructure.Direction = DMA_DIR_PERIPH_DST;
DMA_InitStructure.BufSize = 8;
DMA_InitStructure.PeriphInc = DMA_PERIPH_INC_DISABLE;
DMA_InitStructure.MemoryInc = DMA_MEM_INC_ENABLE;
DMA_InitStructure.PeriphDataSize = DMA_PERIPH_DATA_WIDTH_WORD;
DMA_InitStructure.MemDataSize = DMA_MEM_DATA_WIDTH_WORD;
DMA_InitStructure.CircularMode = DMA_MODE_NORMAL;
DMA_InitStructure.Priority = DMA_PRIORITY_HIGH;
DMA_InitStructure.Mem2Mem = DMA_M2M_DISABLE;
DMA_Init(DMA1_CH5, &DMA_InitStructure);
DMA_RequestRemap(DMA_REMAP_ATIM1_UP,DMA1_CH5, ENABLE);
3. Poll the transfer completion flag. After the channel is enabled it waits for TC5 to be set, then clears the global and per-channel flags.
src/main.csrc/main.c · main
/* DMA1 Channel5 enable */
DMA_EnableChannel(DMA1_CH5, ENABLE);
/* Wait until DMA1 Channel5 end of Transfer */
while (!DMA_GetFlagStatus(DMA_FLAG_TC5, DMA1))
{
}
DMA_ClearFlag(DMA_FLAG_GL5 | DMA_FLAG_TC5 | DMA_FLAG_HT5 | DMA_FLAG_TE5, DMA1);
4. The background loop repeats the whole burst. When DmaAgain is set, the burst and DMA are reconfigured, then the channel is started to wait for the end of transfer.
src/main.csrc/main.c · main
while (1)
{
if (DmaAgain)
{
DmaAgain = 0;
TIM_ConfigDma(TIMx, TIM_DMABASE_CAPCMPDAT1, TIM_DMABURST_LENGTH_8TRANSFERS);
TIM_EnableDma(TIMx, TIM_DMA_UPDATE, ENABLE);
DMA_Configuration();
/* DMA1 Channel5 enable */
DMA_EnableChannel(DMA1_CH5, ENABLE);
/* Wait until DMA1 Channel5 end of Transfer */
while (!DMA_GetFlagStatus(DMA_FLAG_TC5, DMA1))
{
}
DMA_ClearFlag(DMA_FLAG_GL5 | DMA_FLAG_TC5 | DMA_FLAG_HT5 | DMA_FLAG_TE5, DMA1);
}
}
Corresponding source files: src/main.c
5.27.3.7 ExtTrigger_Synchro external trigger synchronization
Example directory: projects/n32h49x_EVAL/examples/TIM/ExtTrigger_Synchro/
Enable the ATIM1, GTIM5, GTIM6, and pin clocks→Configure the three CH1 and the TI2 pins→Set the three timers to the same time base and configure toggle output→TIMx uses TI2 for gated triggering and outputs an enable event→GTIM5 and GTIM6 receive the trigger stage by stage→Enable the counters and apply the external trigger
| Item | Source analysis |
|---|---|
| Function | ATIM1 starts and stops counting on the external rising edge of CH2 (TI2), and CH1 outputs in toggle mode; the enable event of ATIM1 gates GTIM5 and GTIM6 stage by stage, forming external-trigger-driven cascade synchronization. |
| Source files | src/main.c: clock and GPIO configuration, and the time base, toggle output, input capture, and master/slave mode configuration of the three timers;inc/main.h: TIMx is ATIM1, TIMy is GTIM5, TIMz is GTIM6, and the CH1 and CH2 pin macros of each channel;src/n32h49x_it.c and inc/n32h49x_it.h: interrupt handlers;readme.txt: function, environment, and usage;MDK-ARM/ and EWARM/: Keil and IAR projects. |
| Key configuration | Timers: TIMx is ATIM1, TIMy is GTIM5, and TIMz is GTIM6, all with Period 73, Prescaler 2, and ClkDiv DIV1;Channels: the three CH1 channels are all OCMODE_TOGGLE, and the TIMx Pulse is 64;Trigger: the TIMx trigger input selects TI2FP2 and enters gated slave mode, the trigger output selects the enable event, TIMy selects ITR0, and TIMz selects ITR12; Input capture: TIMx CH2 rising edge, direct mapping, no prescaler, and filter 0; Pins: ATIM1 CH1=PA8, CH2=PA9, GTIM5 CH1=PA2, GTIM6 CH1=PD5. |
| Program and data path | main first sets the same time base for the three timers, then configures the TIMx toggle output and TI2 input capture and sets TIMx to gated slave mode with the enable event as the trigger output;TIMy and TIMz receive the trigger of the previous stage through ITR0 and ITR12 respectively; finally the TIMx main output is turned on and the three counters are enabled, and the external trigger edge propagates stage by stage. |
| Main APIs | TIM_InitTimBaseStruct, TIM_InitTimeBase, TIM_InitOcStruct, TIM_InitOc1, TIM_InitIcStruct, TIM_ICInit, TIM_SelectInputTrig, TIM_SelectSlaveMode, TIM_SelectMasterSlaveMode, TIM_SelectOutputTrig, TIM_EnableCtrlPwmOutputs, TIM_Enable |
| Verification | Apply a rising-edge pulse to PA9 (TI2) with a signal generator and observe PA8, PA2, and PD5 with an oscilloscope; each external trigger starts and stops the three timer stages at the same time, and the three toggle outputs change with the trigger edge. |
| Use note | The development environment is KEIL MDK-ARM 5.34 or IAR EWARM 8.50.1; based on the full-function board N32H497ZGL7_EVB V1.0 at HSI+PLL 240 MHz; the external trigger signal must be connected to the TI2 pin, and its frequency kept within the range allowed by the timer input. |
Core-code walkthrough and porting
The example makes the gated start and stop of ATIM1 depend on the external trigger, and then passes this enable event to the general-purpose timers stage by stage.
Data path: TI2 rising edge → ATIM1 gated slave mode starts and stops counting → the ATIM1 enable event as the trigger output → GTIM5 (ITR0) → GTIM6 (ITR12).
1. The three timers use the same time base. The period of TIMx, TIMy, and TIMz is 73 and the prescaler is 2.
src/main.csrc/main.c · main
/* Time base configuration */
TIM_InitTimBaseStruct(&TIM_TimeBaseStructure);
TIM_TimeBaseStructure.Period = 73;
TIM_TimeBaseStructure.Prescaler = 2;
TIM_TimeBaseStructure.ClkDiv = TIM_CLK_DIV1;
TIM_TimeBaseStructure.CounterMode = TIM_CNT_MODE_UP;
TIM_InitTimeBase(TIMx, &TIM_TimeBaseStructure);
TIM_TimeBaseStructure.Period = 73;
TIM_InitTimeBase(TIMy, &TIM_TimeBaseStructure);
TIM_TimeBaseStructure.Period = 73;
TIM_InitTimeBase(TIMz, &TIM_TimeBaseStructure);
2. TIMx is configured for toggle output and uses TI2 as the gated trigger. CH1 outputs in toggle mode, CH2 is mapped directly for input capture, and the trigger input selects TI2FP2 and enters gated slave mode.
src/main.csrc/main.c · main
/* Master Configuration in Toggle Mode */
TIM_InitOcStruct(&TIM_OCInitStructure);
TIM_OCInitStructure.OCMode = TIM_OCMODE_TOGGLE;
TIM_OCInitStructure.OutputState = TIM_OUTPUT_STATE_ENABLE;
TIM_OCInitStructure.Pulse = 64;
TIM_OCInitStructure.OCPolarity = TIM_OC_POLARITY_HIGH;
TIM_InitOc1(TIMx, &TIM_OCInitStructure);
/* TIMx Input Capture Configuration */
TIM_InitIcStruct(&TIM_ICInitStructure);
TIM_ICInitStructure.Channel = TIM_CH_2;
TIM_ICInitStructure.ICPolarity = TIM_IC_POLARITY_RISING;
TIM_ICInitStructure.ICSelection = TIM_IC_SELECTION_DIRECTTI;
TIM_ICInitStructure.ICPrescaler = TIM_IC_PSC_DIV1;
TIM_ICInitStructure.ICFilter = 0;
TIM_ICInit(TIMx, &TIM_ICInitStructure);
/* TIMx Input trigger configuration: External Trigger connected to TI2 */
TIM_SelectInputTrig(TIMx, TIM_TRIG_SEL_TI2FP2);
TIM_SelectSlaveMode(TIMx, TIM_SLAVE_MODE_GATED);
/* Select the Master Slave Mode */
TIM_SelectMasterSlaveMode(TIMx, TIM_MASTER_SLAVE_MODE_ENABLE);
/* Master Mode selection: TIMx */
TIM_SelectOutputTrig(TIMx, TIM_TRGO_SRC_ENABLE);
3. The enable event is passed down stage by stage. The TIMx trigger output selects the enable event, and TIMy and TIMz receive it through ITR0 and ITR12 respectively.
src/main.csrc/main.c · main
/* Slave Mode selection: TIMy */
TIM_SelectInputTrig(TIMy, TIM_TRIG_SEL_IN_TR0);
TIM_SelectSlaveMode(TIMy, TIM_SLAVE_MODE_GATED);
/* Select the Master Slave Mode */
TIM_SelectMasterSlaveMode(TIMy, TIM_MASTER_SLAVE_MODE_ENABLE);
/* Master Mode selection: TIMy */
TIM_SelectOutputTrig(TIMy, TIM_TRGO_SRC_ENABLE);
/* Slave Mode selection: TIMz */
TIM_SelectInputTrig(TIMz, TIM_TRIG_SEL_IN_TR12);
TIM_SelectSlaveMode(TIMz, TIM_SLAVE_MODE_GATED);
4. Clock and pin enable. The three timers are on AHB and APB1 respectively, and the four pins are distributed on GPIOA and GPIOD.
src/main.csrc/main.c · RCC_Configuration
/* TIMx, GPIOx and AFIO clocks enable */
RCC_EnableAHBPeriphClk(TIMx_CLK,ENABLE);
RCC_EnableAPB1PeriphClk(TIMy_CLK | TIMz_CLK,ENABLE);
RCC_EnableAHB1PeriphClk(TIMx_CH1_GPIO_CLK | TIMx_CH2_GPIO_CLK |\
TIMy_CH1_GPIO_CLK | TIMz_CH1_GPIO_CLK,ENABLE);
RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPHEN_AFIO,ENABLE);
Corresponding source files: src/main.c
5.27.3.8 InputCapture input capture frequency measurement
Example directory: projects/n32h49x_EVAL/examples/TIM/InputCapture/
Enable the GTIM5 and GPIO clocks→Configure the CH2 input capture and the PA3 output pin→Enable the CC2 capture interrupt and the counter→PA3 produces two rising edges→The capture interrupt records the two capture values→Convert the difference into the period and frequency
| Item | Source analysis |
|---|---|
| Function | GTIM5 CH2 measures the period of the pulse output on PA3 in input capture mode and computes the frequency in the CC2 interrupt; after gOnePulsEn is set to 1, PA3 produces two rising edges, and the difference of the capture values is the measured period. |
| Source files | src/main.c: clock, GPIO, and NVIC configuration, the CH2 input capture, and the pulse generation function;src/n32h49x_it.c: TIMx_IRQHandler reads the two capture values and computes the frequency;inc/main.h: TIMx is GTIM5, the CH2 pin macro, the interrupt number, and the global variable declarations;readme.txt: function, environment, and usage;MDK-ARM/ and EWARM/: Keil and IAR projects. |
| Key configuration | Timer: TIMx is GTIM5, using the default time base;Input capture: CH2 rising edge, direct mapping, no prescaler, filter 0, and the CC2 interrupt enabled; Pins: CH2=PD2 (alternate function) and PA3 (push-pull output for generating the measured pulse); Interrupt: GTIM5_IRQn preemption 1 and subpriority 0; Computation: the frequency is SystemCoreClock/2 divided by the difference of the two capture values, wrapping at 0xFFFF across zero. |
| Program and data path | main configures the CH2 input capture and the CC2 interrupt, enables the counter, and then calls GenTwoRisingEdge in a loop;when gOnePulsEn is set to 1, GenTwoRisingEdge produces two rising edges on PA3;TIMx_IRQHandler captures the two rising edges one after another and computes the period and frequency from the difference. |
| Main APIs | TIM_InitIcStruct, TIM_ICInit, TIM_ClrIntPendingBit, TIM_ConfigInt, TIM_Enable, TIM_GetIntStatus, TIM_GetCap2 |
| Verification | After gOnePulsEn is set to 1, observe the two rising edges on PA3 and the capture input on PD2 with an oscilloscope;the period and frequency results can be seen in the Capture and TIMxFreq variables. |
| Use note | The development environment is KEIL MDK-ARM 5.34 or IAR EWARM 8.50.1; based on the full-function board N32H497ZGL7_EVB V1.0 at HSI+PLL 240 MHz; the measured period must not exceed the full counter range, otherwise the capture prescaler or the wrap-around logic must be used. |
Core-code walkthrough and porting
The example measures the period of one pulse with the input capture channel of a general-purpose timer and computes the frequency in the interrupt.
Data path: PA3 output pulse → GTIM5 CH2 input capture → the CC2 interrupt records the two capture values → the difference is converted into period and frequency.
1. CH2 is configured as rising-edge input capture and the CC2 interrupt is enabled. Direct mapping, no prescaler, filter 0, and the CC2 interrupt is turned on after the flags are cleared.
src/main.csrc/main.c · main
TIM_InitIcStruct(&TIM_ICInitStructure);
TIM_ICInitStructure.Channel = TIM_CH_2;
TIM_ICInitStructure.ICPolarity = TIM_IC_POLARITY_RISING;
TIM_ICInitStructure.ICSelection = TIM_IC_SELECTION_DIRECTTI;
TIM_ICInitStructure.ICPrescaler = TIM_IC_PSC_DIV1;
TIM_ICInitStructure.ICFilter = 0x0;
TIM_ICInit(TIMx, &TIM_ICInitStructure);
TIM_ClrIntPendingBit(TIMx,TIM_INT_UPDATE);
TIM_ClrIntPendingBit(TIMx,TIM_INT_CC2);
/* Enable the CC2 Interrupt Request */
TIM_ConfigInt(TIMx, TIM_INT_CC2, ENABLE);
/* TIM enable counter */
TIM_Enable(TIMx, ENABLE);
2. A push-pull output pin generates the measured pulse. The CH2 pin is configured as an alternate function, and PA3 as a push-pull output for generating the signal.
src/main.csrc/main.c · GPIO_Configuration
/* GPIOx Configuration: Pin of TIMx */
GPIO_InitStructure.Pin = TIMx_CH2_GPIO_PIN;
GPIO_InitStructure.GPIO_Mode = GPIO_MODE_AF_PP;
GPIO_InitStructure.GPIO_Slew_Rate = GPIO_SLEW_RATE_SLOW;
GPIO_InitStructure.GPIO_Alternate = TIMx_CH2_GPIO_AF;
GPIO_InitPeripheral(TIMx_CH2_GPIO_PORT, &GPIO_InitStructure);
/* GPIOx Configuration: Pin of TIMx */
GPIO_InitStructure.Pin = GPIO_PIN_3;
GPIO_InitStructure.GPIO_Mode = GPIO_MODE_OUTPUT_PP;
GPIO_InitPeripheral(GPIOA, &GPIO_InitStructure);
3. The capture interrupt computes the period from two capture values. The first value is stored as the start, the second is subtracted from it, wrapping at 0xFFFF across zero, and the frequency is then computed.
src/n32h49x_it.csrc/n32h49x_it.c · TIMx_IRQHandler
void TIMx_IRQHandler(void)
{
if (TIM_GetIntStatus(TIMx, TIM_INT_CC2) == SET)
{
TIMxEnterIrqCnt++;
/* Clear TIMx Capture compare interrupt pending bit */
TIM_ClrIntPendingBit(TIMx, TIM_INT_CC2);
if (CaptureNumber == 0)
{
/* Get the Input Capture value */
IC3ReadValue1 = TIM_GetCap2(TIMx);
CaptureNumber = 1;
}
else if (CaptureNumber == 1)
{
/* Get the Input Capture value */
IC3ReadValue2 = TIM_GetCap2(TIMx);
/* Capture computation */
if (IC3ReadValue2 > IC3ReadValue1)
{
Capture = (IC3ReadValue2 - IC3ReadValue1);
}
else
{
Capture = ((0xFFFF - IC3ReadValue1) + IC3ReadValue2);
}
/* Frequency computation */
TIMxFreq = (uint32_t)(SystemCoreClock/2) / Capture;
CaptureNumber = 0;
}
}
}
4. A small flag drives the pulse output. When gOnePulsEn is set to 1, two rising edges are output on PA3 for CH2 to capture.
src/main.csrc/main.c · GenTwoRisingEdge
void GenTwoRisingEdge(void)
{
if (gOnePulsEn)
{
gOnePulsEn = 0;
GPIO_SetBits(GPIOA, GPIO_PIN_3);
{
volatile uint32_t i = 0;
while (i++ < 10)
;
}
GPIO_ResetBits(GPIOA, GPIO_PIN_3);
{
volatile uint32_t i = 0;
while (i++ < 10)
;
}
GPIO_SetBits(GPIOA, GPIO_PIN_3);
{
volatile uint32_t i = 0;
while (i++ < 10)
;
}
GPIO_ResetBits(GPIOA, GPIO_PIN_3);
}
}
Corresponding source files: src/main.c, src/n32h49x_it.c
5.27.3.9 OCActive output compare active level
Example directory: projects/n32h49x_EVAL/examples/TIM/OCActive/
Enable the GTIM1 clock and the four channel pins→Compute the prescaler value and configure the time base→Configure the four channels in active level mode→Disable the four output compare preloads→Enable the auto-reload preload and the counter→Observe the four waveforms toggling one after another
| Item | Source analysis |
|---|---|
| Function | All four output compare channels of GTIM1 are set to active level mode, with compare values 1000, 500, 250, and 125; when the counter reaches the corresponding compare value the channel switches to the active level and stays there, and the four delays increase in turn. |
| Source files | src/main.c: clock and GPIO configuration, and the GTIM1 time base and four output compare channels;inc/main.h: TIMx is GTIM1, and the pin macros of the four channels;src/n32h49x_it.c and inc/n32h49x_it.h: interrupt handlers;readme.txt: function, environment, and usage;MDK-ARM/ and EWARM/: Keil and IAR projects. |
| Key configuration | Timer: TIMx is GTIM1, Prescaler derived from (SystemCoreClock/2)/2000-1, Period 65535, and ClkDiv DIV1;Channels: CH1 to CH4 are all OCMODE_ACTIVE, the compare values are 1000/500/250/125, the outputs are enabled, and the polarity is high;Preload: the four output compare preloads are disabled and the auto-reload preload is enabled; Pins: CH1=PA5, CH2=PA1, CH3=PA2, CH4=PA3, all alternate push-pull; Clock: the counting clock is a beat of about 2 kHz after dividing SystemCoreClock/2. |
| Program and data path | main first computes the prescaler value and configures the time base, then configures the four output compare channels in turn and disables their preloads;then it enables the auto-reload preload and the counter; the four compare values are fixed constants, and when the counter reaches each one the corresponding channel switches to the active level. |
| Main APIs | TIM_InitTimBaseStruct, TIM_InitTimeBase, TIM_InitOcStruct, TIM_InitOc1, TIM_InitOc2, TIM_InitOc3, TIM_InitOc4, TIM_ConfigOc1Preload, TIM_ConfigOc2Preload, TIM_ConfigOc3Preload, TIM_ConfigOc4Preload, TIM_ConfigArPreload, TIM_Enable |
| Verification | Observe PA5, PA1, PA2, and PA3 at the same time with an oscilloscope; each channel switches to the active level when the counter reaches its compare value, and a smaller compare value switches earlier. |
| Use note | The development environment is KEIL MDK-ARM 5.34 or IAR EWARM 8.50.1; based on the full-function board N32H497ZGL7_EVB V1.0 at HSI+PLL 240 MHz; the four channels share one counter, and the compare values determine their switch times, so keep the compare values smaller than the period when changing them. |
Core-code walkthrough and porting
The example makes the four output compare channels switch to the active level one after another within the same counting period, to demonstrate the active level mode.
Data path: prescaled counting clock → the counter increments → compared with the four compare values one by one → the corresponding channel switches to the active level.
1. The prescaler value is computed from the system clock. The counting clock is SystemCoreClock/2, prescaled to about 2 kHz, and the period is 65535.
src/main.csrc/main.c · main
/*Compute the prescaler value */
PrescalerValue = (uint16_t)((SystemCoreClock/2)/2000) - 1;
/* Time base configuration */
TIM_InitTimBaseStruct(&TIM_TimeBaseStructure);
TIM_TimeBaseStructure.Period = 65535;
TIM_TimeBaseStructure.Prescaler = PrescalerValue;
TIM_TimeBaseStructure.ClkDiv = TIM_CLK_DIV1;
TIM_TimeBaseStructure.CounterMode = TIM_CNT_MODE_UP;
TIM_InitTimeBase(TIMx, &TIM_TimeBaseStructure);
2. All four channels use active level mode and their preloads are disabled. The compare values are 1000/500/250/125, and disabling the preload makes the compare values take effect immediately.
src/main.csrc/main.c · main
/* Output Compare Active Mode configuration: Channel1 */
TIM_InitOcStruct(&TIM_OCInitStructure);
TIM_OCInitStructure.OCMode = TIM_OCMODE_ACTIVE;
TIM_OCInitStructure.OutputState = TIM_OUTPUT_STATE_ENABLE;
TIM_OCInitStructure.Pulse = CCR1_Val;
TIM_OCInitStructure.OCPolarity = TIM_OC_POLARITY_HIGH;
TIM_InitOc1(TIMx, &TIM_OCInitStructure);
TIM_ConfigOc1Preload(TIMx, TIM_OC_PRE_LOAD_DISABLE);
/* Output Compare Active Mode configuration: Channel2 */
TIM_OCInitStructure.OutputState = TIM_OUTPUT_STATE_ENABLE;
TIM_OCInitStructure.Pulse = CCR2_Val;
TIM_InitOc2(TIMx, &TIM_OCInitStructure);
TIM_ConfigOc2Preload(TIMx, TIM_OC_PRE_LOAD_DISABLE);
/* Output Compare Active Mode configuration: Channel3 */
TIM_OCInitStructure.OutputState = TIM_OUTPUT_STATE_ENABLE;
TIM_OCInitStructure.Pulse = CCR3_Val;
TIM_InitOc3(TIMx, &TIM_OCInitStructure);
TIM_ConfigOc3Preload(TIMx, TIM_OC_PRE_LOAD_DISABLE);
/* Output Compare Active Mode configuration: Channel4 */
TIM_OCInitStructure.OutputState = TIM_OUTPUT_STATE_ENABLE;
TIM_OCInitStructure.Pulse = CCR4_Val;
TIM_InitOc4(TIMx, &TIM_OCInitStructure);
TIM_ConfigOc4Preload(TIMx, TIM_OC_PRE_LOAD_DISABLE);
3. Auto-reload preload and counter enable. The auto-reload preload is turned on and then the counter is enabled.
src/main.csrc/main.c · main
TIM_ConfigArPreload(TIMx, ENABLE);
/* TIM3 enable counter */
TIM_Enable(TIMx, ENABLE);
4. The four output pins are all alternate push-pull. CH1 to CH4 correspond to PA5, PA1, PA2, and PA3.
src/main.csrc/main.c · GPIO_Configuration
/* GPIOx Configuration: Pin of TIMx */
GPIO_InitStructure.Pin = TIMx_CH1_GPIO_PIN;
GPIO_InitStructure.GPIO_Mode = GPIO_MODE_AF_PP;
GPIO_InitStructure.GPIO_Slew_Rate = GPIO_SLEW_RATE_SLOW;
GPIO_InitStructure.GPIO_Alternate = TIMx_CH1_GPIO_AF;
GPIO_InitPeripheral(TIMx_CH1_GPIO_PORT, &GPIO_InitStructure);
GPIO_InitStructure.Pin = TIMx_CH2_GPIO_PIN;
GPIO_InitStructure.GPIO_Alternate = TIMx_CH2_GPIO_AF;
GPIO_InitPeripheral(TIMx_CH2_GPIO_PORT, &GPIO_InitStructure);
GPIO_InitStructure.Pin = TIMx_CH3_GPIO_PIN;
GPIO_InitStructure.GPIO_Alternate = TIMx_CH3_GPIO_AF;
GPIO_InitPeripheral(TIMx_CH3_GPIO_PORT, &GPIO_InitStructure);
GPIO_InitStructure.Pin = TIMx_CH4_GPIO_PIN;
GPIO_InitStructure.GPIO_Alternate = TIMx_CH4_GPIO_AF;
GPIO_InitPeripheral(TIMx_CH4_GPIO_PORT, &GPIO_InitStructure);
Corresponding source files: src/main.c
5.27.3.10 OCInactive output compare inactive level
Example directory: projects/n32h49x_EVAL/examples/TIM/OCInactive/
Enable the GTIM2, GPIO, and NVIC clocks and interrupt→Configure PA1 to PA4 as push-pull outputs→Compute the prescaler value and configure the time base→Configure the four channels in inactive level mode→Enable the four compare interrupts and set the pins high→The interrupt resets the corresponding pin per channel
| Item | Source analysis |
|---|---|
| Function | The four output compare channels of GTIM2 are set to inactive level mode, and an interrupt is triggered when the counter reaches each compare value; the interrupt resets PA1 to PA4 to low level respectively, demonstrating the combination of compare events and software reset. |
| Source files | src/main.c: clock, NVIC, and GPIO configuration, and the GTIM2 time base and four output compare channels;src/n32h49x_it.c: GTIM2_IRQHandler clears the flag and resets the pin per channel;inc/main.h: macros such as the pins and interrupt number;readme.txt: function, environment, and usage;MDK-ARM/ and EWARM/: Keil and IAR projects. |
| Key configuration | Timer: TIMx is GTIM2, Prescaler derived from (SystemCoreClock/2)/2000-1, Period 65535, and ClkDiv DIV1;Channels: CH1 to CH4 are all OCMODE_INACTIVE, the compare values are 1000/500/250/125, the outputs are enabled, and the polarity is high;Preload: the four output compare preloads are disabled and the auto-reload preload is enabled; Interrupt: the CC1 to CC4 interrupts are enabled, and GTIM2_IRQn preemption is 1 with subpriority 0; Pins: PA1 to PA4 are push-pull outputs and are set by software before startup. |
| Program and data path | main configures the time base and the four inactive level channels, enables the four capture/compare interrupts, and then sets PA1 to PA4;when the counter reaches each compare value the corresponding channel generates a compare event, and GTIM2_IRQHandler clears the flag and resets the corresponding pin per channel;the four compare values differ, so the pins are reset to low level at different times. |
| Main APIs | TIM_InitTimBaseStruct, TIM_InitTimeBase, TIM_InitOcStruct, TIM_InitOc1, TIM_InitOc2, TIM_InitOc3, TIM_InitOc4, TIM_ConfigOc1Preload, TIM_ConfigArPreload, TIM_ConfigInt, TIM_Enable, TIM_GetIntStatus, TIM_ClrIntPendingBit |
| Verification | Observe PA1 to PA4 with an oscilloscope; the four pins are set high at power-up and are reset to low level by the interrupt one after another when the counter reaches each compare value. |
| Use note | The development environment is KEIL MDK-ARM 5.34 or IAR EWARM 8.50.1; based on the full-function board N32H497ZGL7_EVB V1.0 at HSI+PLL 240 MHz; after resetting the pin in the interrupt, clear the corresponding flag to avoid re-entry, and when several channels share an interrupt judge them by channel. |
Core-code walkthrough and porting
The example makes the four output compare events trigger interrupts one after another within the counting period, and the interrupt resets the corresponding pin to low level.
Data path: counting clock → compared with the four compare values → the corresponding CCx interrupt → resets PA1 to PA4.
1. The prescaler and time base are fixed. The counting clock is SystemCoreClock/2 divided to about 2 kHz, and the period is 65535.
src/main.csrc/main.c · main
/* Compute the prescaler value */
PrescalerValue = (uint16_t)((SystemCoreClock/2)/ 2000) - 1;
/* Time base configuration */
TIM_InitTimBaseStruct(&TIM_TimeBaseStructure);
TIM_TimeBaseStructure.Period = 65535;
TIM_TimeBaseStructure.Prescaler = PrescalerValue;
TIM_TimeBaseStructure.ClkDiv = TIM_CLK_DIV1;
TIM_TimeBaseStructure.CounterMode = TIM_CNT_MODE_UP;
TIM_InitTimeBase(GTIM2, &TIM_TimeBaseStructure);
2. All four channels use inactive level mode and their preloads are disabled. The compare values are 1000/500/250/125, and disabling the preload makes the compare values take effect immediately.
src/main.csrc/main.c · main
/* Output Compare Active Mode configuration: Channel1 */
TIM_InitOcStruct(&TIM_OCInitStructure);
TIM_OCInitStructure.OCMode = TIM_OCMODE_INACTIVE;
TIM_OCInitStructure.OutputState = TIM_OUTPUT_STATE_ENABLE;
TIM_OCInitStructure.Pulse = CCR1_Val;
TIM_OCInitStructure.OCPolarity = TIM_OC_POLARITY_HIGH;
TIM_InitOc1(GTIM2, &TIM_OCInitStructure);
TIM_ConfigOc1Preload(GTIM2, TIM_OC_PRE_LOAD_DISABLE);
/* Output Compare Active Mode configuration: Channel2 */
TIM_OCInitStructure.OutputState = TIM_OUTPUT_STATE_ENABLE;
TIM_OCInitStructure.Pulse = CCR2_Val;
TIM_InitOc2(GTIM2, &TIM_OCInitStructure);
TIM_ConfigOc2Preload(GTIM2, TIM_OC_PRE_LOAD_DISABLE);
/* Output Compare Active Mode configuration: Channel3 */
TIM_OCInitStructure.OutputState = TIM_OUTPUT_STATE_ENABLE;
TIM_OCInitStructure.Pulse = CCR3_Val;
TIM_InitOc3(GTIM2, &TIM_OCInitStructure);
TIM_ConfigOc3Preload(GTIM2, TIM_OC_PRE_LOAD_DISABLE);
/* Output Compare Active Mode configuration: Channel4 */
TIM_OCInitStructure.OutputState = TIM_OUTPUT_STATE_ENABLE;
TIM_OCInitStructure.Pulse = CCR4_Val;
TIM_InitOc4(GTIM2, &TIM_OCInitStructure);
TIM_ConfigOc4Preload(GTIM2, TIM_OC_PRE_LOAD_DISABLE);
3. The four compare interrupts are enabled and the pins set high. The CC1 to CC4 interrupts are enabled, PA1 to PA4 are set before startup, and then the counter is enabled.
src/main.csrc/main.c · main
/* TIM IT enable */
TIM_ConfigInt(GTIM2, TIM_INT_CC1 | TIM_INT_CC2 | TIM_INT_CC3 | TIM_INT_CC4, ENABLE);
/* Set output pins */
GPIO_SetBits(GPIOA, GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_3 | GPIO_PIN_4);
/* TIM2 enable counter */
TIM_Enable(GTIM2, ENABLE);
4. The interrupt clears the flag and resets the pin per channel. When each compare event arrives it clears the corresponding flag and resets the corresponding pin.
src/n32h49x_it.csrc/n32h49x_it.c · GTIM2_IRQHandler
void GTIM2_IRQHandler(void)
{
if (TIM_GetIntStatus(GTIM2, TIM_INT_CC1) != RESET)
{
/* Clear GTIM2 Capture Compare1 interrupt pending bit*/
TIM_ClrIntPendingBit(GTIM2, TIM_INT_CC1);
GPIO_ResetBits(GPIOA, GPIO_PIN_1);
}
else if (TIM_GetIntStatus(GTIM2, TIM_INT_CC2) != RESET)
{
/* Clear GTIM2 Capture Compare2 interrupt pending bit*/
TIM_ClrIntPendingBit(GTIM2, TIM_INT_CC2);
GPIO_ResetBits(GPIOA, GPIO_PIN_2);
}
else if (TIM_GetIntStatus(GTIM2, TIM_INT_CC3) != RESET)
{
/* Clear GTIM2 Capture Compare3 interrupt pending bit*/
TIM_ClrIntPendingBit(GTIM2, TIM_INT_CC3);
GPIO_ResetBits(GPIOA, GPIO_PIN_3);
}
else
{
/* Clear GTIM2 Capture Compare4 interrupt pending bit*/
TIM_ClrIntPendingBit(GTIM2, TIM_INT_CC4);
GPIO_ResetBits(GPIOA, GPIO_PIN_4);
}
}
Corresponding source files: src/main.c, src/n32h49x_it.c
5.27.3.11 OCToggle output compare toggle
Example directory: projects/n32h49x_EVAL/examples/TIM/OCToggle/
Enable the GTIM1 clock and the four channel pins→Compute the prescaler value and configure the time base→Configure the four channels in toggle mode→Disable the preload and clear the interrupt flags→Enable the four compare interrupts and the counter→The interrupt dynamically rewrites the next toggle point
| Item | Source analysis |
|---|---|
| Function | The four output compare channels of GTIM1 are set to toggle mode, with a period of 0xFFFFFFFF; each compare interrupt sets the next compare value to the current count plus CCRx_Val, producing four square waves of different frequencies. |
| Source files | src/main.c: clock, GPIO, and NVIC configuration, and the GTIM1 time base and four toggle channels;src/n32h49x_it.c: TIMx_IRQHandler updates the compare value of each channel in the interrupt;inc/main.h: TIMx is GTIM1, the four pin macros, and the interrupt number;readme.txt: function, environment, and usage;MDK-ARM/ and EWARM/: Keil and IAR projects. |
| Key configuration | Timer: TIMx is GTIM1, Prescaler derived from (SystemCoreClock/2)/6000000-1, Period 0xFFFFFFFF, and ClkDiv DIV1;Channels: CH1 to CH4 are all OCMODE_TOGGLE, the initial compare values are 32768/16384/8192/4096, the outputs are enabled, and the polarity is low;Preload: the four output compare preloads are disabled; Interrupt: the CC1 to CC4 interrupts are enabled, and GTIM1_IRQn preemption is 1 with subpriority 0; Pins: CH1=PA5, CH2=PA1, CH3=PA2, CH4=PA3. |
| Program and data path | main configures the time base and the four toggle channels, disables the preload, and clears the flags, then enables the four compare interrupts and the counter;TIMx_IRQHandler reads the current count on each compare event and adds the corresponding CCRx_Val, writing it back to the compare register to form the next toggle point;the four compare increments differ, so the output frequencies differ too. |
| Main APIs | TIM_InitTimBaseStruct, TIM_InitTimeBase, TIM_InitOcStruct, TIM_InitOc1, TIM_InitOc2, TIM_InitOc3, TIM_InitOc4, TIM_ConfigOc1Preload, TIM_ClrIntPendingBit, TIM_ConfigInt, TIM_Enable, TIM_GetIntStatus, TIM_GetCap1, TIM_SetCmp1 |
| Verification | Observe PA5, PA1, PA2, and PA3 with an oscilloscope; the four toggle outputs have different frequencies, and a larger compare increment gives a longer period. |
| Use note | The development environment is KEIL MDK-ARM 5.34 or IAR EWARM 8.50.1; based on the full-function board N32H497ZGL7_EVB V1.0 at HSI+PLL 240 MHz; in toggle mode the compare value must be updated in time in the interrupt; leaving it unupdated for a long time makes the output stay at a fixed level. |
Core-code walkthrough and porting
The example uses output compare toggle mode to make four channels produce square waves of different frequencies, with the toggle points updated dynamically by the interrupt.
Data path: counting clock → compare match → CCx interrupt → read the current count plus CCRx_Val and write it back to the compare register → the channel toggles.
1. The prescaler and time base cover the whole counting range. The counting clock is SystemCoreClock/2 divided to 6 MHz, and the period is 0xFFFFFFFF.
src/main.csrc/main.c · main
/* Compute the prescaler value */
PrescalerValue = (uint16_t)((SystemCoreClock/2)/ 6000000) - 1;
/* Time base configuration */
TIM_InitTimBaseStruct(&TIM_TimeBaseStructure);
TIM_TimeBaseStructure.Period = 0xFFFFFFFF;
TIM_TimeBaseStructure.Prescaler = PrescalerValue;
TIM_TimeBaseStructure.ClkDiv = TIM_CLK_DIV1;
TIM_TimeBaseStructure.CounterMode = TIM_CNT_MODE_UP;
TIM_InitTimeBase(TIMx, &TIM_TimeBaseStructure);
2. All four channels use toggle mode and their preloads are disabled. The initial compare values are 32768/16384/8192/4096, and disabling the preload makes the compare values take effect immediately.
src/main.csrc/main.c · main
/* Output Compare Toggle Mode configuration: Channel1 */
TIM_InitOcStruct(&TIM_OCInitStructure);
TIM_OCInitStructure.OCMode = TIM_OCMODE_TOGGLE;
TIM_OCInitStructure.OutputState = TIM_OUTPUT_STATE_ENABLE;
TIM_OCInitStructure.Pulse = CCR1_Val;
TIM_OCInitStructure.OCPolarity = TIM_OC_POLARITY_LOW;
TIM_InitOc1(TIMx, &TIM_OCInitStructure);
TIM_ConfigOc1Preload(TIMx, TIM_OC_PRE_LOAD_DISABLE);
/* Output Compare Toggle Mode configuration: Channel2 */
TIM_OCInitStructure.OutputState = TIM_OUTPUT_STATE_ENABLE;
TIM_OCInitStructure.Pulse = CCR2_Val;
TIM_InitOc2(TIMx, &TIM_OCInitStructure);
TIM_ConfigOc2Preload(TIMx, TIM_OC_PRE_LOAD_DISABLE);
/* Output Compare Toggle Mode configuration: Channel3 */
TIM_OCInitStructure.OutputState = TIM_OUTPUT_STATE_ENABLE;
TIM_OCInitStructure.Pulse = CCR3_Val;
TIM_InitOc3(TIMx, &TIM_OCInitStructure);
TIM_ConfigOc3Preload(TIMx, TIM_OC_PRE_LOAD_DISABLE);
/* Output Compare Toggle Mode configuration: Channel4 */
TIM_OCInitStructure.OutputState = TIM_OUTPUT_STATE_ENABLE;
TIM_OCInitStructure.Pulse = CCR4_Val;
TIM_InitOc4(TIMx, &TIM_OCInitStructure);
TIM_ConfigOc4Preload(TIMx, TIM_OC_PRE_LOAD_DISABLE);
3. Clear the flags and then enable the four compare interrupts and the counter. The update flag and the four CC flags are cleared first, then the interrupts and counting are enabled.
src/main.csrc/main.c · main
TIM_ClrIntPendingBit(TIMx, TIM_INT_UPDATE);
TIM_ClrIntPendingBit(TIMx, TIM_INT_CC1);
TIM_ClrIntPendingBit(TIMx, TIM_INT_CC2);
TIM_ClrIntPendingBit(TIMx, TIM_INT_CC3);
TIM_ClrIntPendingBit(TIMx, TIM_INT_CC4);
/* TIM IT enable */
TIM_ConfigInt(TIMx, TIM_INT_CC1 | TIM_INT_CC2 | TIM_INT_CC3 | TIM_INT_CC4, ENABLE);
/* TIM enable counter */
TIM_Enable(TIMx, ENABLE);
4. The interrupt dynamically rewrites the next toggle point. On each compare event the current count is read and the corresponding increment added, and the result is written back to the compare register.
src/n32h49x_it.csrc/n32h49x_it.c · TIMx_IRQHandler
void TIMx_IRQHandler(void)
{
/* TIMx_CH1 toggling */
if (TIM_GetIntStatus(TIMx, TIM_INT_CC1) != RESET)
{
TIM_ClrIntPendingBit(TIMx, TIM_INT_CC1);
capture = TIM_GetCap1(TIMx);
TIM_SetCmp1(TIMx, capture + CCR1_Val);
}
/* TIMx_CH2 toggling */
if (TIM_GetIntStatus(TIMx, TIM_INT_CC2) != RESET)
{
TIM_ClrIntPendingBit(TIMx, TIM_INT_CC2);
capture = TIM_GetCap2(TIMx);
TIM_SetCmp2(TIMx, capture + CCR2_Val);
}
/* TIMx_CH3 toggling */
if (TIM_GetIntStatus(TIMx, TIM_INT_CC3) != RESET)
{
TIM_ClrIntPendingBit(TIMx, TIM_INT_CC3);
capture = TIM_GetCap3(TIMx);
TIM_SetCmp3(TIMx, capture + CCR3_Val);
}
/* TIM3_CH4 toggling */
if (TIM_GetIntStatus(TIMx, TIM_INT_CC4) != RESET)
{
TIM_ClrIntPendingBit(TIMx, TIM_INT_CC4);
capture = TIM_GetCap4(TIMx);
TIM_SetCmp4(TIMx, capture + CCR4_Val);
}
}
Corresponding source files: src/main.c, src/n32h49x_it.c
5.27.3.12 OnePulse one-pulse output
Example directory: projects/n32h49x_EVAL/examples/TIM/OnePulse/
Enable the GTIM1 and channel pin clocks→Configure the counting time base→Configure channel 1 as PWM2 output→Configure channel 2 as input capture→Select one-pulse mode and the trigger source→Set the slave mode to triggered start
| Item | Source analysis |
|---|---|
| Function | GTIM1 is configured in one-pulse mode; an external signal triggers on the rising edge of CH2, and channel 1 outputs one pulse whose width is determined by Period and Pulse. |
| Source files | src/main.c: clock and GPIO configuration, and the one-pulse mode, channel output, and input capture configuration;src/n32h49x_it.c: only exception handlers and empty interrupt entries are kept;inc/main.h: TIMx is GTIM1, and the two pin macros;readme.txt: function, environment, and usage;MDK-ARM/ and EWARM/: Keil and IAR projects. |
| Key configuration | Time base: TIMx is GTIM1, Prescaler derived from (SystemCoreClock/2)/6000000-1, Period 65535, and ClkDiv DIV1;Channel 1: OCMODE_PWM2, compare value 16383, output enabled, and polarity high;Channel 2: rising-edge input capture, direct mapping, no prescaler, and filter 0; Mode: one-pulse single mode, trigger source TI2FP2, and slave mode set to trigger mode; Pins: CH1=PA5, CH2=PA1, and PA3 is a plain push-pull output for manual triggering. |
| Program and data path | main configures the clock, GPIO, time base, the PWM2 output of channel 1, and the input capture of channel 2 in turn, and selects the one-pulse, trigger source, and slave mode settings;the main loop calls the manual trigger send function; when an external rising edge arrives the counter runs once and outputs one pulse, then stops automatically to wait for the next trigger. |
| Main APIs | TIM_InitTimBaseStruct, TIM_InitTimeBase, TIM_InitOcStruct, TIM_InitOc1, TIM_InitIcStruct, TIM_ICInit, TIM_SelectOnePulseMode, TIM_SelectInputTrig, TIM_SelectSlaveMode |
| Verification | Observe PA5 and PA1 with an oscilloscope; for every rising edge received on PA1, PA5 outputs one pulse whose width is proportional to the difference between Period and Pulse. |
| Use note | The development environment is KEIL MDK-ARM 5.34 or IAR EWARM 8.50.1; based on the full-function board N32H497ZGL7_EVB V1.0 at HSI+PLL 240 MHz; in one-pulse mode only one pulse is output per trigger, so continuous output requires repeated trigger edges. |
Core-code walkthrough and porting
The example configures GTIM1 as a one-pulse output triggered by an external rising edge, with the pulse width determined by the difference between the auto-reload value and the compare value.
Data path: external trigger edge → slave mode triggered start of counting → channel 1 PWM2 outputs one pulse → counting stops after reaching Period.
1. The counting clock and time base determine the one-pulse reference. The counting clock is SystemCoreClock/2 divided to 6 MHz, and Period is 65535.
src/main.csrc/main.c · main
/* Compute the prescaler value */
PrescalerValue = (uint16_t)((SystemCoreClock/2) / 6000000) - 1;
/* Time base configuration */
TIM_InitTimBaseStruct(&TIM_TimeBaseStructure);
TIM_TimeBaseStructure.Period = 65535;
TIM_TimeBaseStructure.Prescaler = PrescalerValue;
TIM_TimeBaseStructure.ClkDiv = TIM_CLK_DIV1;
TIM_TimeBaseStructure.CounterMode = TIM_CNT_MODE_UP;
TIM_InitTimeBase(TIMx, &TIM_TimeBaseStructure);
2. Channel 1 outputs the one pulse in PWM2. The compare value is 16383, and the difference between Period and Pulse is the count corresponding to the one-pulse width.
src/main.csrc/main.c · main
/* TIMx PWM2 Mode configuration: Channel1 */
TIM_InitOcStruct(&TIM_OCInitStructure);
TIM_OCInitStructure.OCMode = TIM_OCMODE_PWM2;
TIM_OCInitStructure.OutputState = TIM_OUTPUT_STATE_ENABLE;
TIM_OCInitStructure.Pulse = 16383;
TIM_OCInitStructure.OCPolarity = TIM_OC_POLARITY_HIGH;
TIM_InitOc1(TIMx, &TIM_OCInitStructure);
3. Channel 2 is configured for rising-edge capture and the trigger source and slave mode are selected. The capture polarity is rising, direct mapping, no prescaler, filter 0, the trigger source is TI2FP2, and the slave mode is trigger mode.
src/main.csrc/main.c · main
TIM_InitIcStruct(&TIM_ICInitStructure);
TIM_ICInitStructure.Channel = TIM_CH_2;
TIM_ICInitStructure.ICPolarity = TIM_IC_POLARITY_RISING;
TIM_ICInitStructure.ICSelection = TIM_IC_SELECTION_DIRECTTI;
TIM_ICInitStructure.ICPrescaler = TIM_IC_PSC_DIV1;
TIM_ICInitStructure.ICFilter = 0;
TIM_ICInit(TIMx, &TIM_ICInitStructure);
/* One Pulse Mode selection */
TIM_SelectOnePulseMode(TIMx, TIM_OPMODE_SINGLE);
/* Input Trigger selection */
TIM_SelectInputTrig(TIMx, TIM_TRIG_SEL_TI2FP2);
/* Slave Mode selection: Trigger Mode */
TIM_SelectSlaveMode(TIMx, TIM_SLAVE_MODE_TRIG);
Corresponding source files: src/main.c
5.27.3.13 Parallel_Synchro parallel synchronization
Example directory: projects/n32h49x_EVAL/examples/TIM/Parallel_Synchro/
Enable the three timer and pin clocks→Configure the master timer time base and PWM1→The master timer uses the update event as the trigger output→Configure the slave timer time base and PWM1→The slave timers select gated mode and the input trigger→Enable the slave timers first and then the master timer
| Item | Source analysis |
|---|---|
| Function | GTIM2 acts as the master timer and outputs PWM, triggered by the update event; GTIM5 and GTIM6 act as slave timers in gated mode, with start and stop controlled by the master trigger signal. |
| Source files | src/main.c: clock and GPIO configuration, and the master/slave timers, PWM1 output, and gated trigger configuration;src/n32h49x_it.c: only exception-handler entries are kept;inc/main.h: TIMx/TIMy/TIMz are GTIM2/GTIM5/GTIM6, and the three pin macros;readme.txt: function, environment, and usage;MDK-ARM/ and EWARM/: Keil and IAR projects. |
| Key configuration | Master timer: TIMx is GTIM2, Period 255, Prescaler 0, PWM1, compare value 64, master/slave mode enabled, and trigger output on the update event;Slave timers: TIMy is GTIM5 (Period 9) and TIMz is GTIM6 (Period 4), both PWM1 with compare value 3;Slave mode: both slave timers are in gated mode with input trigger ITR2; Pins: GTIM2_CH1=PA6, GTIM5_CH1=PA2, GTIM6_CH1=PD5. |
| Program and data path | main configures the three time bases and PWM1 outputs, the master timer outputs the update event and enables master/slave mode, and the two slave timers select gated mode and the ITR2 trigger;the slave timers are enabled first and then the master timer; each update event of the master timer controls the slave count, and the slave timers output PWM with their own period and compare values. |
| Main APIs | TIM_InitTimBaseStruct, TIM_InitTimeBase, TIM_InitOcStruct, TIM_InitOc1, TIM_SelectMasterSlaveMode, TIM_SelectOutputTrig, TIM_SelectSlaveMode, TIM_SelectInputTrig, TIM_Enable |
| Verification | Observe PA6, PA2, and PD5 with an oscilloscope; the slave output frequency is an integer division of the master frequency, and the duty cycle is determined by each compare value. |
| Use note | The development environment is KEIL MDK-ARM 5.34 or IAR EWARM 8.50.1; based on the full-function board N32H497ZGL7_EVB V1.0 at HSI+PLL 240 MHz; in gated mode the slave timers count only while the master trigger is active, and enabling the slave timers before the master avoids losing triggers during startup. |
Core-code walkthrough and porting
The example uses the update event of one master timer to trigger two gated slave timers in parallel, outputting divided PWM in phase with the master timer.
Data path: master timer counting → update event → trigger output → slave timer gated enable → slave timer counts and outputs PWM.
1. The three time bases lay the foundation for synchronization. The master timer Period is 255, and the two slave timers use 9 and 4.
src/main.csrc/main.c · main
/* Time base configuration */
TIM_InitTimBaseStruct(&TIM_TimeBaseStructure);
TIM_TimeBaseStructure.Period = 255;
TIM_TimeBaseStructure.Prescaler = 0;
TIM_TimeBaseStructure.ClkDiv = TIM_CLK_DIV1;
TIM_TimeBaseStructure.CounterMode = TIM_CNT_MODE_UP;
TIM_InitTimeBase(TIMx, &TIM_TimeBaseStructure);
TIM_TimeBaseStructure.Period = 9;
TIM_InitTimeBase(TIMy, &TIM_TimeBaseStructure);
TIM_TimeBaseStructure.Period = 4;
TIM_InitTimeBase(TIMz, &TIM_TimeBaseStructure);
2. The master timer uses PWM1 and outputs the update event. The compare value is 64, and after master/slave mode is enabled the trigger output selects the update event.
src/main.csrc/main.c · main
/* Master Configuration in PWM1 Mode */
TIM_InitOcStruct(&TIM_OCInitStructure);
TIM_OCInitStructure.OCMode = TIM_OCMODE_PWM1;
TIM_OCInitStructure.OutputState = TIM_OUTPUT_STATE_ENABLE;
TIM_OCInitStructure.Pulse = 64;
TIM_OCInitStructure.OCPolarity = TIM_OC_POLARITY_HIGH;
TIM_InitOc1(TIMx, &TIM_OCInitStructure);
/* Select the Master Slave Mode */
TIM_SelectMasterSlaveMode(TIMx, TIM_MASTER_SLAVE_MODE_ENABLE);
/* Master Mode selection */
TIM_SelectOutputTrig(TIMx, TIM_TRGO_SRC_UPDATE);
3. The two slave timers are configured for PWM1 and gated triggering. The compare value is 3, the slave mode is gated, and the input trigger selects ITR2.
src/main.csrc/main.c · main
/* Slaves Configuration: PWM1 Mode */
TIM_OCInitStructure.OCMode = TIM_OCMODE_PWM1;
TIM_OCInitStructure.OutputState = TIM_OUTPUT_STATE_ENABLE;
TIM_OCInitStructure.Pulse = 3;
TIM_InitOc1(TIMy, &TIM_OCInitStructure);
TIM_InitOc1(TIMz, &TIM_OCInitStructure);
/* Slave Mode selection: TIMy */
TIM_SelectSlaveMode(TIMy, TIM_SLAVE_MODE_GATED);
TIM_SelectInputTrig(TIMy, TIM_TRIG_SEL_IN_TR2);
/* Slave Mode selection: TIMz */
TIM_SelectSlaveMode(TIMz, TIM_SLAVE_MODE_GATED);
TIM_SelectInputTrig(TIMz, TIM_TRIG_SEL_IN_TR2);
4. Enable the slave timers first and then the master timer. This makes sure the slave timers are ready before the trigger arrives.
src/main.csrc/main.c · main
/* TIM enable counter */
TIM_Enable(TIMy, ENABLE);
TIM_Enable(TIMx, ENABLE);
TIM_Enable(TIMz, ENABLE);
Corresponding source files: src/main.c
5.27.3.14 PWM_Input PWM input capture
Example directory: projects/n32h49x_EVAL/examples/TIM/PWM_Input/
Enable the GTIM1 and channel pin clocks→Configure the PWM input capture→Select the input trigger and reset slave mode→Enable the counter and the CC2 interrupt→The main loop produces a square wave on PA3→The capture interrupt computes duty cycle and frequency
| Item | Source analysis |
|---|---|
| Function | GTIM1 works in PWM input mode; an external PWM is input from CH2, the hardware uses two captures to obtain the period and the high-level width respectively, and the interrupt computes the frequency and duty cycle. |
| Source files | src/main.c: clock, GPIO, and NVIC configuration, and the PWM input capture and slave mode configuration;src/n32h49x_it.c: TIMx_IRQHandler computes the duty cycle and frequency;inc/main.h: TIMx is GTIM1, and the pin and interrupt macros;readme.txt: function, environment, and usage;MDK-ARM/ and EWARM/: Keil and IAR projects. |
| Key configuration | Timer: TIMx is GTIM1;Capture: channel 2 rising edge, direct mapping, no prescaler, filter 0, and the PWM input method occupies two captures at once; Slave mode: input trigger TI2FP2, reset mode, and master/slave mode enabled; Interrupt: the CC2 interrupt is enabled, and GTIM1_IRQn preemption is 1 with subpriority 0; Pins: CH2=PA1, and PA3 is a plain push-pull output used as the signal source. |
| Program and data path | main configures the PWM input capture, the input trigger, the reset slave mode, and master/slave enable, then enables the counter and the CC2 interrupt;the main loop produces a square wave on PA3 that can be fed back to PA1; each CC2 capture interrupt reads the capture values and uses CC2 for the period and frequency and CC1 for the duty cycle. |
| Main APIs | TIM_InitIcStruct, TIM_ConfigPwmIc, TIM_SelectInputTrig, TIM_SelectSlaveMode, TIM_SelectMasterSlaveMode, TIM_Enable, TIM_ConfigInt, TIM_ClrIntPendingBit, TIM_GetCap2, TIM_GetCap1 |
| Verification | Observe with an oscilloscope or debug variables; if the square wave on PA3 is fed back to PA1, the frequency and duty cycle in the interrupt change with the square wave. |
| Use note | The development environment is KEIL MDK-ARM 5.34 or IAR EWARM 8.50.1; based on the full-function board N32H497ZGL7_EVB V1.0 at HSI+PLL 240 MHz; PWM input mode needs an external signal on CH2, and for verification the square wave produced on PA3 by this example can be fed back. |
Core-code walkthrough and porting
The example uses one PWM input capture to measure both the period and the high-level width of the input signal, obtaining the frequency and the duty cycle.
Data path: external PWM → CH2 rising edge → CC2 captures the period and CC1 captures the high level → the CC2 interrupt computes the frequency and duty cycle.
1. The PWM input method occupies two captures at once. Channel 2 rising edge, direct mapping, no prescaler, filter 0, configured by TIM_ConfigPwmIc.
src/main.csrc/main.c · main
TIM_InitIcStruct(&TIM_ICInitStructure);
TIM_ICInitStructure.Channel = TIM_CH_2;
TIM_ICInitStructure.ICPolarity = TIM_IC_POLARITY_RISING;
TIM_ICInitStructure.ICSelection = TIM_IC_SELECTION_DIRECTTI;
TIM_ICInitStructure.ICPrescaler = TIM_IC_PSC_DIV1;
TIM_ICInitStructure.ICFilter = 0x0;
TIM_ConfigPwmIc(TIMx, &TIM_ICInitStructure);
2. The input trigger and reset slave mode are selected and counting is started. Reset slave mode clears the counter on each rising edge, which makes the period easy to measure.
src/main.csrc/main.c · main
/* Select the TIM3 Input Trigger: TI2FP2 */
TIM_SelectInputTrig(TIMx, TIM_TRIG_SEL_TI2FP2);
/* Select the slave Mode: Reset Mode */
TIM_SelectSlaveMode(TIMx, TIM_SLAVE_MODE_RESET);
/* Enable the Master/Slave Mode */
TIM_SelectMasterSlaveMode(TIMx, TIM_MASTER_SLAVE_MODE_ENABLE);
/* TIM enable counter */
TIM_Enable(TIMx, ENABLE);
/* Enable the CC2 Interrupt Request */
TIM_ConfigInt(TIMx, TIM_INT_CC2, ENABLE);
3. The CC2 interrupt is enabled and computes the frequency and duty cycle. The CC2 capture value gives the period and frequency, and the CC1 capture value gives the duty cycle.
src/n32h49x_it.csrc/n32h49x_it.c · TIMx_IRQHandler
void TIMx_IRQHandler(void)
{
/* Clear TIMx Capture compare interrupt pending bit */
TIM_ClrIntPendingBit(TIMx, TIM_INT_CC2);
/* Get the Input Capture value */
IC2Value = TIM_GetCap2(TIMx);
if (IC2Value != 0)
{
/* Duty cycle computation */
DutyCycle = (TIM_GetCap1(TIMx) * 100) / IC2Value;
/* Frequency computation */
Frequency = SystemCoreClock / IC2Value;
}
else
{
DutyCycle = 0;
Frequency = 0;
}
}
Corresponding source files: src/main.c, src/n32h49x_it.c
5.27.3.15 PWM_Output PWM output
Example directory: projects/n32h49x_EVAL/examples/TIM/PWM_Output/
Enable the GTIM1 and four pin clocks→Compute the prescaler and configure the time base→Configure the four channels as PWM1→Enable the output compare preload of each channel→Enable the auto-reload preload→Enable the counter
| Item | Source analysis |
|---|---|
| Function | The four channels of GTIM1 output PWM with four different duty cycles; the period is fixed and the compare values differ, so PA5/PA1/PA2/PA3 get duty cycles of about 50%, 25%, 12.5%, and 6.25%. |
| Source files | src/main.c: clock and GPIO configuration, and the four PWM1 outputs and preload configuration;src/n32h49x_it.c: only exception-handler entries are kept;inc/main.h: TIMx is GTIM1, and the four pin macros;readme.txt: function, environment, and usage;MDK-ARM/ and EWARM/: Keil and IAR projects. |
| Key configuration | Timer: TIMx is GTIM1, Prescaler derived from SystemCoreClock/12000000-1, Period 1200, and ClkDiv DIV1;Channels: CH1 to CH4 are all OCMODE_PWM1, the compare values are 600/300/150/75, the outputs are enabled, and the polarity is high;Preload: the four output compare preloads are enabled and the auto-reload preload is enabled; Pins: CH1=PA5, CH2=PA1, CH3=PA2, CH4=PA3. |
| Program and data path | main computes the prescaler and configures the time base, then configures all four channels as PWM1 with their compare values, and finally enables the preloads and the counter;the duty cycle is determined by the ratio of the compare value to Period; the output frequency is determined by the counting clock and Period. |
| Main APIs | TIM_InitTimBaseStruct, TIM_InitTimeBase, TIM_InitOcStruct, TIM_InitOc1, TIM_InitOc2, TIM_InitOc3, TIM_InitOc4, TIM_ConfigOc1Preload, TIM_ConfigOc2Preload, TIM_ConfigOc3Preload, TIM_ConfigOc4Preload, TIM_ConfigArPreload, TIM_Enable |
| Verification | Observe PA5, PA1, PA2, and PA3 with an oscilloscope; the four channels have the same period and the duty cycles halve in turn. |
| Use note | The development environment is KEIL MDK-ARM 5.34 or IAR EWARM 8.50.1; based on the full-function board N32H497ZGL7_EVB V1.0 at HSI+PLL 240 MHz; when the output compare preload is enabled a new compare value takes effect at the update event, so rewriting it at runtime produces no glitches. |
Core-code walkthrough and porting
The example uses one time base to make four channels output PWM of the same frequency and different duty cycles, with the compare values rewritable at runtime.
Data path: counting clock → compared with the compare value of each channel → four PWM1 channels output different duty cycles.
1. One time base defines the period of the four PWM channels. The counting clock is SystemCoreClock/12000000 giving 12 MHz, and Period is 1200.
src/main.csrc/main.c · main
PrescalerValue = (uint32_t)(SystemCoreClock / 12000000) - 1;
/* Time base configuration */
TIM_InitTimBaseStruct(&TIM_TimeBaseStructure);
TIM_TimeBaseStructure.Period = 1200;
TIM_TimeBaseStructure.Prescaler = PrescalerValue;
TIM_TimeBaseStructure.ClkDiv = TIM_CLK_DIV1;
TIM_TimeBaseStructure.CounterMode = TIM_CNT_MODE_UP;
TIM_InitTimeBase(TIMx, &TIM_TimeBaseStructure);
2. All four channels are configured for PWM1 with different compare values. The compare values are 600/300/150/75, the outputs are enabled with high polarity, and the output compare preload of each channel is turned on.
src/main.csrc/main.c · main
/* PWM1 Mode configuration: Channel1 */
TIM_InitOcStruct(&TIM_OCInitStructure);
TIM_OCInitStructure.OCMode = TIM_OCMODE_PWM1;
TIM_OCInitStructure.OutputState = TIM_OUTPUT_STATE_ENABLE;
TIM_OCInitStructure.Pulse = CCR1_Val;
TIM_OCInitStructure.OCPolarity = TIM_OC_POLARITY_HIGH;
TIM_InitOc1(TIMx, &TIM_OCInitStructure);
TIM_ConfigOc1Preload(TIMx, TIM_OC_PRE_LOAD_ENABLE);
/* PWM1 Mode configuration: Channel2 */
TIM_OCInitStructure.OutputState = TIM_OUTPUT_STATE_ENABLE;
TIM_OCInitStructure.Pulse = CCR2_Val;
TIM_InitOc2(TIMx, &TIM_OCInitStructure);
TIM_ConfigOc2Preload(TIMx, TIM_OC_PRE_LOAD_ENABLE);
/* PWM1 Mode configuration: Channel3 */
TIM_OCInitStructure.OutputState = TIM_OUTPUT_STATE_ENABLE;
TIM_OCInitStructure.Pulse = CCR3_Val;
TIM_InitOc3(TIMx, &TIM_OCInitStructure);
TIM_ConfigOc3Preload(TIMx, TIM_OC_PRE_LOAD_ENABLE);
/* PWM1 Mode configuration: Channel4 */
TIM_OCInitStructure.OutputState = TIM_OUTPUT_STATE_ENABLE;
TIM_OCInitStructure.Pulse = CCR4_Val;
TIM_InitOc4(TIMx, &TIM_OCInitStructure);
TIM_ConfigOc4Preload(TIMx, TIM_OC_PRE_LOAD_ENABLE);
3. The auto-reload preload is enabled and then counting is started. The auto-reload value also uses preload, so writing Period takes effect at the update event.
src/main.csrc/main.c · main
TIM_ConfigArPreload(TIMx, ENABLE);
/* TIMx enable counter */
TIM_Enable(TIMx, ENABLE);
Corresponding source files: src/main.c
5.27.3.16 Quadrature_Output quadrature output
Example directory: projects/n32h49x_EVAL/examples/TIM/Quadrature_Output/
Enable the clocks and pins→Configure the four PWM2 outputs of GTIM7→Configure the time base of the four slave timers respectively→The slave timers select trigger slave mode and the input trigger→Enable the advanced timer main outputs→Enable the GTIM7 counter
| Item | Source analysis |
|---|---|
| Function | The four channels of GTIM7 trigger the CH1 outputs of ATIM1, ATIM2, GTIM8, and GTIM9 respectively; the four outputs have phase differences of 90, 180, and 270 degrees relative to the reference in turn. |
| Source files | src/main.c: clock and GPIO configuration, and the four PWM2 channels of the master timer and the four slave timers;src/n32h49x_it.c: only exception-handler entries are kept;inc/main.h: the four pin macros;readme.txt: function, environment, and usage;MDK-ARM/ and EWARM/: Keil and IAR projects. |
| Key configuration | Master timer: GTIM7, Period 1199, PWM2, and four compare values 149/299/449/599;Slave timers: ATIM1 and ATIM2 have CapCh2Sel 1, GTIM8 and GTIM9 have 4, and all four have Period 599, PWM2, and compare value 299;Slave mode: all four are in trigger mode with input trigger TI2FP2; Output: the four timers enable the main output with TIM_EnableCtrlPwmOutputs;Pins: PC0, PD14, PB14, PA6. |
| Program and data path | main first configures the four PWM2 trigger sources of GTIM7, then configures the four slave timers, and finally enables the main outputs and the GTIM7 count;each compare event of GTIM7 starts one output of the corresponding slave timer through the input trigger; the slave timers select different capture channel mappings, forming a phase difference in steps of 90 degrees. |
| Main APIs | TIM_InitTimBaseStruct, TIM_InitTimeBase, TIM_InitOcStruct, TIM_InitOc1, TIM_InitOc2, TIM_InitOc3, TIM_InitOc4, TIM_SelectSlaveMode, TIM_SelectInputTrig, TIM_EnableCtrlPwmOutputs, TIM_Enable |
| Verification | Observe PC0, PD14, PB14, and PA6 with an oscilloscope; the four waveforms have the same frequency and pairwise phase differences of 90, 180, and 270 degrees. |
| Use note | The development environment is KEIL MDK-ARM 5.34 or IAR EWARM 8.50.1; based on the full-function board N32H497ZGL7_EVB V1.0 at HSI+PLL 240 MHz; the advanced timer output also needs the main output enabled (MOEN), otherwise the channel pins produce no waveform. |
Core-code walkthrough and porting
The example makes the four channels of one general-purpose timer trigger four other timers, producing several outputs with phase steps of 90 degrees.
Data path: the four GTIM7 compare events → trigger the slave timers → the slave timers count with the selected capture mapping → multiphase PWM output.
1. GTIM7 uses four PWM2 channels as the trigger source. The four compare values are 149/299/449/599, providing the phase reference for the four outputs.
src/main.csrc/main.c · GTIM7_Configuration
/* Time Base configuration */
PrescalerValue = (uint32_t)(SystemCoreClock / 12000000) - 1;
TIM_InitTimBaseStruct(&TIM_TimeBaseStructure);
TIM_TimeBaseStructure.Period = 1199;
TIM_TimeBaseStructure.Prescaler = PrescalerValue;
TIM_TimeBaseStructure.ClkDiv = TIM_CLK_DIV1;
TIM_TimeBaseStructure.CounterMode = TIM_CNT_MODE_UP;
TIM_InitTimeBase(GTIM7, &TIM_TimeBaseStructure);
/* Channel 1 Configuration in PWM mode */
TIM_InitOcStruct(&TIM_OCInitStructure);
TIM_OCInitStructure.OCMode = TIM_OCMODE_PWM2;
TIM_OCInitStructure.OutputState = TIM_OUTPUT_STATE_ENABLE;
TIM_OCInitStructure.Pulse = 149;
TIM_OCInitStructure.OCPolarity = TIM_OC_POLARITY_HIGH;
TIM_InitOc1(GTIM7, &TIM_OCInitStructure);
/* Channel 2 Configuration in PWM mode */
TIM_OCInitStructure.Pulse = 299;
TIM_InitOc2(GTIM7, &TIM_OCInitStructure);
/* Channel 3 Configuration in PWM mode */
TIM_OCInitStructure.Pulse = 449;
TIM_InitOc3(GTIM7, &TIM_OCInitStructure);
/* Channel 4 Configuration in PWM mode */
TIM_OCInitStructure.Pulse = 599;
TIM_InitOc4(GTIM7, &TIM_OCInitStructure);
2. ATIM1 uses capture mapping 1 and selects trigger slave mode. The time-base Period is 599 with PWM2 and compare value 299, the slave mode is trigger mode, and the input trigger selects TI2FP2.
src/main.csrc/main.c · ATIM1_Configuration
/* Time Base configuration */
TIM_InitTimBaseStruct(&TIM_TimeBaseStructure);
TIM_TimeBaseStructure.CapCh2Sel = TIM_CAPCH2SEL_1;
TIM_TimeBaseStructure.Prescaler = PrescalerValue;
TIM_TimeBaseStructure.CounterMode = TIM_CNT_MODE_UP;
TIM_TimeBaseStructure.Period = 599;
TIM_TimeBaseStructure.ClkDiv = TIM_CLK_DIV1;
TIM_TimeBaseStructure.RepetCnt = 0;
TIM_InitTimeBase(ATIM1, &TIM_TimeBaseStructure);
/* Channel 1 Configuration in PWM mode */
TIM_InitOcStruct(&TIM_OCInitStructure);
TIM_OCInitStructure.OCMode = TIM_OCMODE_PWM2;
TIM_OCInitStructure.OutputState = TIM_OUTPUT_STATE_ENABLE;
TIM_OCInitStructure.OutputNState = TIM_OUTPUT_NSTATE_DISABLE;
TIM_OCInitStructure.Pulse = 299;
TIM_OCInitStructure.OCPolarity = TIM_OC_POLARITY_LOW;
TIM_OCInitStructure.OCNPolarity = TIM_OCN_POLARITY_LOW;
TIM_OCInitStructure.OCIdleState = TIM_OC_IDLE_STATE_SET;
TIM_OCInitStructure.OCNIdleState = TIM_OCN_IDLE_STATE_RESET;
TIM_InitOc1(ATIM1, &TIM_OCInitStructure);
TIM_SelectSlaveMode(ATIM1, TIM_SLAVE_MODE_TRIG);
TIM_SelectInputTrig(ATIM1, TIM_TRIG_SEL_TI2FP2);
3. Enable the main outputs and start GTIM7. The four slave timers enable MOEN with the main output enable, and finally the GTIM7 count is enabled.
src/main.csrc/main.c · main
/* Enable MOEN */
TIM_EnableCtrlPwmOutputs(ATIM1, ENABLE);
TIM_EnableCtrlPwmOutputs(ATIM2, ENABLE);
TIM_EnableCtrlPwmOutputs(GTIM8, ENABLE);
TIM_EnableCtrlPwmOutputs(GTIM9, ENABLE);
/* Enable GTIM7 */
TIM_Enable(GTIM7, ENABLE);
Corresponding source files: src/main.c
5.27.3.17 TimeBase output compare timing
Example directory: projects/n32h49x_EVAL/examples/TIM/TimeBase/
Enable the GTIM2 and output pin clocks→Configure the time base and prescaler→Configure the four channels in output compare timing mode→Disable the preload of each channel→Enable the four compare interrupts and the counter→The interrupt toggles the GPIO and changes the compare value
| Item | Source analysis |
|---|---|
| Function | GTIM2 uses output compare timing mode to produce four timings at different rates; each compare event toggles the corresponding GPIO in the interrupt and adds the next compare value, producing four software timers. |
| Source files | src/main.c: clock, GPIO, and NVIC configuration, and the four output compare timing channels;src/n32h49x_it.c: GTIM2_IRQHandler toggles the GPIO and updates the compare value;inc/main.h: function declarations;readme.txt: function, environment, and usage;MDK-ARM/ and EWARM/: Keil and IAR projects. |
| Key configuration | Timer: GTIM2, Period 65535, Prescaler derived from (SystemCoreClock/2)/12000000-1, and ClkDiv DIV1;Channels: CH1 to CH4 are all OCMODE_TIMING, the compare values are 40961/27309/13654/6826, the outputs are enabled with high polarity, and the preload is disabled;Interrupt: the CC1 to CC4 interrupts are enabled, and GTIM2_IRQn preemption is 1 with subpriority 0; Pins: PC6 to PC9 are plain push-pull outputs toggled by the interrupt. |
| Program and data path | main configures the time base and prescaler, sets all four channels to output compare timing mode and disables the preload, then enables the four compare interrupts and counting;GTIM2_IRQHandler checks the interrupt per channel, toggles the corresponding GPIO, and writes the current count plus CCRx_Val back to the compare register;the four compare increments differ, so the toggle rates differ too. |
| Main APIs | TIM_InitTimBaseStruct, TIM_InitTimeBase, TIM_ConfigPrescaler, TIM_InitOcStruct, TIM_InitOc1, TIM_InitOc4, TIM_ConfigOc1Preload, TIM_ConfigOc4Preload, TIM_ConfigInt, TIM_Enable, TIM_GetIntStatus, TIM_ClrIntPendingBit, TIM_GetCap1, TIM_SetCmp1 |
| Verification | Observe PC6 to PC9 with an oscilloscope; the four toggle rates are inversely proportional to their compare increments. |
| Use note | The development environment is KEIL MDK-ARM 5.34 or IAR EWARM 8.50.1; based on the full-function board N32H497ZGL7_EVB V1.0 at HSI+PLL 240 MHz; output compare timing mode needs the next compare value rewritten in the interrupt each time, otherwise it toggles only once. |
Core-code walkthrough and porting
The example uses output compare timing mode with interrupts to make four software-timed outputs at different rates on the same counter.
Data path: counting clock → compare match → CCx interrupt → toggle the GPIO and write back the next compare value.
1. The time base and prescaler determine the counting rate. The counting clock is SystemCoreClock/2 divided to 12 MHz; Period 65535 is written first with the time-base structure, then the prescaler is written with an immediate reload through TIM_ConfigPrescaler.
src/main.csrc/main.c · main
/* Compute the prescaler value */
PrescalerValue = (uint16_t)((SystemCoreClock/2)/ 12000000) - 1;
/* Time base configuration */
TIM_InitTimBaseStruct(&TIM_TimeBaseStructure);
TIM_TimeBaseStructure.Period = 65535;
TIM_TimeBaseStructure.Prescaler = 0;
TIM_TimeBaseStructure.ClkDiv = TIM_CLK_DIV1;
TIM_TimeBaseStructure.CounterMode = TIM_CNT_MODE_UP;
TIM_InitTimeBase(GTIM2, &TIM_TimeBaseStructure);
/* Prescaler configuration */
TIM_ConfigPrescaler(GTIM2, PrescalerValue, TIM_PSC_RELOAD_MODE_IMMEDIATE);
2. The four channels are configured for output compare timing mode and their preloads are disabled. The compare values are 40961/27309/13654/6826, and disabling the preload makes the compare values take effect immediately.
src/main.csrc/main.c · main
/* Output Compare Timing Mode configuration: Channel1 */
TIM_InitOcStruct(&TIM_OCInitStructure);
TIM_OCInitStructure.OCMode = TIM_OCMODE_TIMING;
TIM_OCInitStructure.OutputState = TIM_OUTPUT_STATE_ENABLE;
TIM_OCInitStructure.Pulse = CCR1_Val;
TIM_OCInitStructure.OCPolarity = TIM_OC_POLARITY_HIGH;
TIM_InitOc1(GTIM2, &TIM_OCInitStructure);
TIM_ConfigOc1Preload(GTIM2, TIM_OC_PRE_LOAD_DISABLE);
/* Output Compare Timing Mode configuration: Channel2 */
TIM_OCInitStructure.OutputState = TIM_OUTPUT_STATE_ENABLE;
TIM_OCInitStructure.Pulse = CCR2_Val;
TIM_InitOc2(GTIM2, &TIM_OCInitStructure);
TIM_ConfigOc2Preload(GTIM2, TIM_OC_PRE_LOAD_DISABLE);
/* Output Compare Timing Mode configuration: Channel3 */
TIM_OCInitStructure.OutputState = TIM_OUTPUT_STATE_ENABLE;
TIM_OCInitStructure.Pulse = CCR3_Val;
TIM_InitOc3(GTIM2, &TIM_OCInitStructure);
TIM_ConfigOc3Preload(GTIM2, TIM_OC_PRE_LOAD_DISABLE);
/* Output Compare Timing Mode configuration: Channel4 */
TIM_OCInitStructure.OutputState = TIM_OUTPUT_STATE_ENABLE;
TIM_OCInitStructure.Pulse = CCR4_Val;
TIM_InitOc4(GTIM2, &TIM_OCInitStructure);
TIM_ConfigOc4Preload(GTIM2, TIM_OC_PRE_LOAD_DISABLE);
3. Enable the four compare interrupts and toggle the GPIO in the interrupt. On each compare event the corresponding pin is toggled and the current count plus the increment is written back to the compare register.
src/n32h49x_it.csrc/n32h49x_it.c · GTIM2_IRQHandler
void GTIM2_IRQHandler(void)
{
if (TIM_GetIntStatus(GTIM2, TIM_INT_CC1) != RESET)
{
TIM_ClrIntPendingBit(GTIM2, TIM_INT_CC1);
/* Pin PC.06 toggling */
GPIO_WriteBits(GPIOC, GPIO_PIN_6, (Bit_OperateType)(1 - GPIO_ReadOutputDataBit(GPIOC, GPIO_PIN_6)));
capture = TIM_GetCap1(GTIM2);
TIM_SetCmp1(GTIM2, capture + CCR1_Val);
}
else if (TIM_GetIntStatus(GTIM2, TIM_INT_CC2) != RESET)
{
TIM_ClrIntPendingBit(GTIM2, TIM_INT_CC2);
/* Pin PC.07 toggling */
GPIO_WriteBits(GPIOC, GPIO_PIN_7, (Bit_OperateType)(1 - GPIO_ReadOutputDataBit(GPIOC, GPIO_PIN_7)));
capture = TIM_GetCap2(GTIM2);
TIM_SetCmp2(GTIM2, capture + CCR2_Val);
}
else if (TIM_GetIntStatus(GTIM2, TIM_INT_CC3) != RESET)
{
TIM_ClrIntPendingBit(GTIM2, TIM_INT_CC3);
/* Pin PC.08 toggling */
GPIO_WriteBits(GPIOC, GPIO_PIN_8, (Bit_OperateType)(1 - GPIO_ReadOutputDataBit(GPIOC, GPIO_PIN_8)));
capture = TIM_GetCap3(GTIM2);
TIM_SetCmp3(GTIM2, capture + CCR3_Val);
}
else
{
TIM_ClrIntPendingBit(GTIM2, TIM_INT_CC4);
/* Pin PC.09 toggling */
GPIO_WriteBits(GPIOC, GPIO_PIN_9, (Bit_OperateType)(1 - GPIO_ReadOutputDataBit(GPIOC, GPIO_PIN_9)));
capture = TIM_GetCap4(GTIM2);
TIM_SetCmp4(GTIM2, capture + CCR4_Val);
}
}
Corresponding source files: src/main.c, src/n32h49x_it.c
5.27.3.18 TimeBasic_ATIM1 basic timing from the advanced timer
Example directory: projects/n32h49x_EVAL/examples/TIM/TimeBasic_ATIM1/
Enable the ATIM1 and output pin clocks→Configure the time base and prescaler→Enable the update interrupt→Enable the counter→The update interrupt toggles the GPIO
| Item | Source analysis |
|---|---|
| Function | ATIM1 is configured as the most basic up-counting time base; the count overflow generates an update interrupt, and PC6 is toggled in the interrupt to give a square wave of fixed period. |
| Source files | src/main.c: clock, GPIO, and NVIC configuration, and the time base and update interrupt configuration;src/n32h49x_it.c: ATIM1_UP_IRQHandler toggles PC6;inc/main.h: function declarations;readme.txt: function, environment, and usage;MDK-ARM/ and EWARM/: Keil and IAR projects. |
| Key configuration | Timer: ATIM1, Period 65535, Prescaler 0, ClkDiv DIV1, and up-counting;Prescaler: written with an immediate reload through TIM_ConfigPrescaler;Interrupt: the update interrupt is enabled, and ATIM1_UP_IRQn preemption is 1 with subpriority 0; Pin: PC6 is a plain push-pull output toggled by the update interrupt. |
| Program and data path | main configures the clock, GPIO, and NVIC and then calls the timer configuration;TIM_Configuration writes the time-base structure, refreshes the prescaler, enables the update interrupt, and starts counting;each update event toggles PC6 in the interrupt, and the toggle period is twice the counting period. |
| Main APIs | TIM_InitTimBaseStruct, TIM_InitTimeBase, TIM_ConfigPrescaler, TIM_ConfigInt, TIM_Enable, TIM_GetIntStatus, TIM_ClrIntPendingBit |
| Verification | Observe PC6 with an oscilloscope; PC6 outputs a square wave of fixed period, determined by the counting frequency and Period. |
| Use note | The development environment is KEIL MDK-ARM 5.34 or IAR EWARM 8.50.1; based on the full-function board N32H497ZGL7_EVB V1.0 at HSI+PLL 240 MHz; the update interrupt flag must be cleared in the interrupt, otherwise the same interrupt is entered repeatedly. |
Core-code walkthrough and porting
The example is the most basic use of the time base: the counter counts up to Period, generates an update event, and toggles a pin in the interrupt.
Data path: counting clock → counts to Period → update event → the interrupt toggles the GPIO.
1. The time base and prescaler determine the update period. Period is 65535, the prescaler is 0, counting is up, and ClkDiv is DIV1.
src/main.csrc/main.c · TIM_Configuration
/* Time base configuration */
TIM_InitTimBaseStruct(&TIM_TimeBaseStructure);
TIM_TimeBaseStructure.Period = 65535;
TIM_TimeBaseStructure.Prescaler = 0;
TIM_TimeBaseStructure.ClkDiv = TIM_CLK_DIV1;
TIM_TimeBaseStructure.CounterMode = TIM_CNT_MODE_UP;
TIM_InitTimeBase(ATIM1, &TIM_TimeBaseStructure);
/* Prescaler configuration */
TIM_ConfigPrescaler(ATIM1, PrescalerValue, TIM_PSC_RELOAD_MODE_IMMEDIATE);
2. Enable the update interrupt and start counting. TIM_INT_UPDATE is enabled and then the counter is started with TIM_Enable.
src/main.csrc/main.c · TIM_Configuration
/* ATIM1 enable update irq */
TIM_ConfigInt(ATIM1, TIM_INT_UPDATE, ENABLE);
/* ATIM1 enable counter */
TIM_Enable(ATIM1, ENABLE);
3. Toggle the pin in the update interrupt. The update flag is checked, cleared, and PC6 is toggled.
src/n32h49x_it.csrc/n32h49x_it.c · ATIM1_UP_IRQHandler
void ATIM1_UP_IRQHandler(void)
{
if (TIM_GetIntStatus(ATIM1, TIM_INT_UPDATE) != RESET)
{
TIM_ClrIntPendingBit(ATIM1, TIM_INT_UPDATE);
/* IO toggle */
GPIO_WriteBits(GPIOC, GPIO_PIN_6, (Bit_OperateType)(1 - GPIO_ReadOutputDataBit(GPIOC, GPIO_PIN_6)));
}
}
Corresponding source files: src/main.c, src/n32h49x_it.c
5.27.3.19 TimeBasic_BTIM1 basic timing from the basic timer
Example directory: projects/n32h49x_EVAL/examples/TIM/TimeBasic_BTIM1/
Enable the BTIM1 and output pin clocks→Configure the time base and prescaler→Enable the update interrupt→Enable the counter→The update interrupt toggles the GPIO
| Item | Source analysis |
|---|---|
| Function | BTIM1 is configured as the most basic up-counting time base; the count overflow generates an update interrupt, and PC6 is toggled in the interrupt to give a square wave of fixed period. |
| Source files | src/main.c: clock, GPIO, and NVIC configuration, and the time base and update interrupt configuration;src/n32h49x_it.c: BTIM1_IRQHandler toggles PC6;inc/main.h: function declarations;readme.txt: function, environment, and usage;MDK-ARM/ and EWARM/: Keil and IAR projects. |
| Key configuration | Timer: BTIM1, Period 70000, Prescaler 0, ClkDiv DIV1, and up-counting;Prescaler: written with an immediate reload through TIM_ConfigPrescaler;Interrupt: the update interrupt is enabled, and BTIM1_IRQn preemption is 1 with subpriority 0; Pin: PC6 is a plain push-pull output toggled by the update interrupt. |
| Program and data path | main configures the clock, GPIO, and NVIC and then calls the timer configuration;TIM_Configuration writes the time-base structure, refreshes the prescaler, enables the update interrupt, and starts counting;each update event toggles PC6 in the interrupt, and the toggle period is twice the counting period. |
| Main APIs | TIM_InitTimBaseStruct, TIM_InitTimeBase, TIM_ConfigPrescaler, TIM_ConfigInt, TIM_Enable, TIM_GetIntStatus, TIM_ClrIntPendingBit |
| Verification | Observe PC6 with an oscilloscope; PC6 outputs a square wave of fixed period, determined by the counting frequency and Period. |
| Use note | The development environment is KEIL MDK-ARM 5.34 or IAR EWARM 8.50.1; based on the full-function board N32H497ZGL7_EVB V1.0 at HSI+PLL 240 MHz; the basic timer has no external output channel, so its period must be observed by toggling a plain GPIO in the interrupt. |
Core-code walkthrough and porting
The example is the most basic use of the time base: the counter counts up to Period, generates an update event, and toggles a pin in the interrupt.
Data path: counting clock → counts to Period → update event → the interrupt toggles the GPIO.
1. The time base and prescaler determine the update period. Period is 70000, the prescaler is 0, counting is up, and ClkDiv is DIV1.
src/main.csrc/main.c · TIM_Configuration
/* Time base configuration */
TIM_InitTimBaseStruct(&TIM_TimeBaseStructure);
TIM_TimeBaseStructure.Period = 70000;
TIM_TimeBaseStructure.Prescaler = 0;
TIM_TimeBaseStructure.ClkDiv = TIM_CLK_DIV1;
TIM_TimeBaseStructure.CounterMode = TIM_CNT_MODE_UP;
TIM_InitTimeBase(BTIM1, &TIM_TimeBaseStructure);
/* Prescaler configuration */
TIM_ConfigPrescaler(BTIM1, PrescalerValue, TIM_PSC_RELOAD_MODE_IMMEDIATE);
2. Enable the update interrupt and start counting. TIM_INT_UPDATE is enabled and then the counter is started with TIM_Enable.
src/main.csrc/main.c · TIM_Configuration
/* BTIM1 enable update irq */
TIM_ConfigInt(BTIM1, TIM_INT_UPDATE, ENABLE);
/* BTIM1 enable counter */
TIM_Enable(BTIM1, ENABLE);
3. Toggle the pin in the update interrupt. The update flag is checked, cleared, and PC6 is toggled.
src/n32h49x_it.csrc/n32h49x_it.c · BTIM1_IRQHandler
void BTIM1_IRQHandler(void)
{
if (TIM_GetIntStatus(BTIM1, TIM_INT_UPDATE) != RESET)
{
TIM_ClrIntPendingBit(BTIM1, TIM_INT_UPDATE);
/* IO toggle */
GPIO_WriteBits(GPIOC, GPIO_PIN_6, (Bit_OperateType)(1 - GPIO_ReadOutputDataBit(GPIOC, GPIO_PIN_6)));
}
}
Corresponding source files: src/main.c, src/n32h49x_it.c
5.27.3.20 TimeBasic_GTIM2 basic timing from the general-purpose timer
Example directory: projects/n32h49x_EVAL/examples/TIM/TimeBasic_GTIM2/
Enable the GTIM2 and output pin clocks→Configure the time base and prescaler→Enable the update interrupt→Enable the counter→The update interrupt toggles the GPIO
| Item | Source analysis |
|---|---|
| Function | GTIM2 is configured as the most basic up-counting time base; the count overflow generates an update interrupt, and PC6 is toggled in the interrupt to give a square wave of fixed period. |
| Source files | src/main.c: clock, GPIO, and NVIC configuration, and the time base and update interrupt configuration;src/n32h49x_it.c: GTIM2_IRQHandler toggles PC6;inc/main.h: function declarations;readme.txt: function, environment, and usage;MDK-ARM/ and EWARM/: Keil and IAR projects. |
| Key configuration | Timer: GTIM2, Period 65535, Prescaler 0, ClkDiv DIV1, and up-counting;Prescaler: written with an immediate reload through TIM_ConfigPrescaler;Interrupt: the update interrupt is enabled, and GTIM2_IRQn preemption is 1 with subpriority 0; Pin: PC6 is a plain push-pull output toggled by the update interrupt. |
| Program and data path | main configures the clock, GPIO, and NVIC and then calls the timer configuration;TIM_Configuration writes the time-base structure, refreshes the prescaler, enables the update interrupt, and starts counting;each update event toggles PC6 in the interrupt, and the toggle period is twice the counting period. |
| Main APIs | TIM_InitTimBaseStruct, TIM_InitTimeBase, TIM_ConfigPrescaler, TIM_ConfigInt, TIM_Enable, TIM_GetIntStatus, TIM_ClrIntPendingBit |
| Verification | Observe PC6 with an oscilloscope; PC6 outputs a square wave of fixed period, determined by the counting frequency and Period. |
| Use note | The development environment is KEIL MDK-ARM 5.34 or IAR EWARM 8.50.1; based on the full-function board N32H497ZGL7_EVB V1.0 at HSI+PLL 240 MHz; the update interrupt flag must be cleared in the interrupt, otherwise the same interrupt is entered repeatedly. |
Core-code walkthrough and porting
The example is the most basic use of the time base: the counter counts up to Period, generates an update event, and toggles a pin in the interrupt.
Data path: counting clock → counts to Period → update event → the interrupt toggles the GPIO.
1. The time base and prescaler determine the update period. Period is 65535, the prescaler is 0, counting is up, and ClkDiv is DIV1.
src/main.csrc/main.c · TIM_Configuration
/* Time base configuration */
TIM_InitTimBaseStruct(&TIM_TimeBaseStructure);
TIM_TimeBaseStructure.Period = 65535;
TIM_TimeBaseStructure.Prescaler = 0;
TIM_TimeBaseStructure.ClkDiv = TIM_CLK_DIV1;
TIM_TimeBaseStructure.CounterMode = TIM_CNT_MODE_UP;
TIM_InitTimeBase(GTIM2, &TIM_TimeBaseStructure);
/* Prescaler configuration */
TIM_ConfigPrescaler(GTIM2, PrescalerValue, TIM_PSC_RELOAD_MODE_IMMEDIATE);
2. Enable the update interrupt and start counting. TIM_INT_UPDATE is enabled and then the counter is started with TIM_Enable.
src/main.csrc/main.c · TIM_Configuration
/* GTIM2 enable update irq */
TIM_ConfigInt(GTIM2, TIM_INT_UPDATE, ENABLE);
/* GTIM2 enable counter */
TIM_Enable(GTIM2, ENABLE);
3. Toggle the pin in the update interrupt. The update flag is checked, cleared, and PC6 is toggled.
src/n32h49x_it.csrc/n32h49x_it.c · GTIM2_IRQHandler
void GTIM2_IRQHandler(void)
{
if (TIM_GetIntStatus(GTIM2, TIM_INT_UPDATE) != RESET)
{
TIM_ClrIntPendingBit(GTIM2, TIM_INT_UPDATE);
/* Pin PC.06 toggling */
GPIO_WriteBits(GPIOC, GPIO_PIN_6, (Bit_OperateType)(1 - GPIO_ReadOutputDataBit(GPIOC, GPIO_PIN_6)));
}
}
Corresponding source files: src/main.c, src/n32h49x_it.c
5.27.3.21 TimeBasic_GTIM8 basic timing from the general-purpose timer
Example directory: projects/n32h49x_EVAL/examples/TIM/TimeBasic_GTIM8/
Enable the GTIM8 and output pin clocks→Configure the time base and prescaler→Enable the update interrupt→Enable the counter→The update interrupt toggles the GPIO
| Item | Source analysis |
|---|---|
| Function | GTIM8 is configured as the most basic up-counting time base; the count overflow generates an update interrupt, and PC6 is toggled in the interrupt to give a square wave of fixed period. |
| Source files | src/main.c: clock, GPIO, and NVIC configuration, and the time base and update interrupt configuration;src/n32h49x_it.c: GTIM8_IRQHandler toggles PC6;inc/main.h: function declarations;readme.txt: function, environment, and usage;MDK-ARM/ and EWARM/: Keil and IAR projects. |
| Key configuration | Timer: GTIM8, Period 65535, Prescaler 0, ClkDiv DIV1, and up-counting;Bus: GTIM8 is on APB2 and its clock is enabled with RCC_EnableAPB2PeriphClk;Interrupt: the update interrupt is enabled, and GTIM8_IRQn preemption is 1 with subpriority 0; Pin: PC6 is a plain push-pull output toggled by the update interrupt. |
| Program and data path | main configures the clock, GPIO, and NVIC and then calls the timer configuration;TIM_Configuration writes the time-base structure, refreshes the prescaler, enables the update interrupt, and starts counting;each update event toggles PC6 in the interrupt, and the toggle period is twice the counting period. |
| Main APIs | TIM_InitTimBaseStruct, TIM_InitTimeBase, TIM_ConfigPrescaler, TIM_ConfigInt, TIM_Enable, TIM_GetIntStatus, TIM_ClrIntPendingBit |
| Verification | Observe PC6 with an oscilloscope; PC6 outputs a square wave of fixed period, determined by the counting frequency and Period. |
| Use note | The development environment is KEIL MDK-ARM 5.34 or IAR EWARM 8.50.1; based on the full-function board N32H497ZGL7_EVB V1.0 at HSI+PLL 240 MHz; GTIM8 uses a different clock enable function from the timers on APB1, so the clock interface must be changed according to the bus when porting. |
Core-code walkthrough and porting
The example is the most basic use of the time base: the counter counts up to Period, generates an update event, and toggles a pin in the interrupt.
Data path: counting clock → counts to Period → update event → the interrupt toggles the GPIO.
1. The time base and prescaler determine the update period. Period is 65535, the prescaler is 0, counting is up, and ClkDiv is DIV1.
src/main.csrc/main.c · TIM_Configuration
/* Time base configuration */
TIM_InitTimBaseStruct(&TIM_TimeBaseStructure);
TIM_TimeBaseStructure.Period = 65535;
TIM_TimeBaseStructure.Prescaler = 0;
TIM_TimeBaseStructure.ClkDiv = TIM_CLK_DIV1;
TIM_TimeBaseStructure.CounterMode = TIM_CNT_MODE_UP;
TIM_InitTimeBase(GTIM8, &TIM_TimeBaseStructure);
/* Prescaler configuration */
TIM_ConfigPrescaler(GTIM8, PrescalerValue, TIM_PSC_RELOAD_MODE_IMMEDIATE);
2. Enable the update interrupt and start counting. TIM_INT_UPDATE is enabled and then the counter is started with TIM_Enable.
src/main.csrc/main.c · TIM_Configuration
/* GTIM8 enable update irq */
TIM_ConfigInt(GTIM8, TIM_INT_UPDATE, ENABLE);
/* GTIM8 enable counter */
TIM_Enable(GTIM8, ENABLE);
3. Toggle the pin in the update interrupt. The update flag is checked, cleared, and PC6 is toggled.
src/n32h49x_it.csrc/n32h49x_it.c · GTIM8_IRQHandler
void GTIM8_IRQHandler(void)
{
if (TIM_GetIntStatus(GTIM8, TIM_INT_UPDATE) != RESET)
{
TIM_ClrIntPendingBit(GTIM8, TIM_INT_UPDATE);
/* IO toggle */
GPIO_WriteBits(GPIOC, GPIO_PIN_6, (Bit_OperateType)(1 - GPIO_ReadOutputDataBit(GPIOC, GPIO_PIN_6)));
}
}
Corresponding source files: src/main.c, src/n32h49x_it.c
5.27.4 Notes and troubleshooting
| Scenario | Check & action | Source |
|---|---|---|
| Counter does not start in gated or gated+reset mode | In gated mode (including gated+reset), CNTEN must be set first before the trigger input can start the counter.When CNTEN=0, the counter does not start whatever the trigger input level is (user manual, chapter 9, time-base unit). |
User manual |
| Center-aligned mode has no effect | Center-aligned mode is effective only when CAMSEL selects center alignment (not 00).In center-aligned mode the counter direction is updated by hardware and DIR is ignored (user manual, chapter 9, time-base unit). |
User manual |
| Center-aligned combined with asymmetric mode | CAMSEL and the asymmetric mode ASMMETRIC must not be changed at the same time.In asymmetric mode DIR is not writable (user manual, chapter 9, time-base unit). |
User manual |
| Changing the prescaler does not take effect immediately | A new prescaler value written to TIMx_PSC is taken only at the next update event.To make it effective immediately, use the immediate reload mode of TIM_ConfigPrescaler (user manual, chapter 9, prescaler). |
User manual |
| When the auto-reload value is updated | When preload is enabled (ARPEN=1), the auto-reload value is written to the shadow register at the update event.UPDIS=1 can disable the update event (user manual, chapter 9, time-base unit). |
User manual |
| PWM input mode is limited to certain channels | PWM input mode can only be used with TIMx_CH1 and TIMx_CH2.Only TI1FP1 and TI2FP2 are connected to the slave mode controller (user manual, chapter 9, PWM input mode). |
User manual |
| Encoder interface and external clock are mutually exclusive | Encoder interface mode cannot be selected together with external clock mode 2. The encoder interface uses TI1/TI2, and the count direction is controlled automatically by the hardware DIR (user manual, chapter 9, encoder interface mode). |
User manual |
| External clock frequency limit | The input frequency of ETR/external trigger after the prescaler may be higher than the system clock.When TI1/TI2/ITR is used as the external clock, the input frequency must be lower than one quarter of the system clock (user manual, chapters 9 and 11, external clock). |
User manual |
| Clock source in slave mode | In gated, reset, and trigger modes the counter clock can be provided by external clock mode 2.TSEL must select a source other than ETRF (user manual, chapter 9, slave mode). |
User manual |
| Complementary outputs cannot be active at the same time | OCx and OCxN must not be at the active level at the same time, and the expression (CCxP XOR OIx) XOR (CCxNP XOR OIxN) must not be 0 (user manual, chapter 9, break function). |
User manual |
| Output enable while the break input is active | While the break input is active, MOEN cannot be set by hardware or software and BITF cannot be cleared.A delay is required between writing and reading MOEN (user manual, chapter 9, break function). |
User manual |
| Lock configuration can be written only once | LCKCFG can be written only once after an MCU reset.After reset the break circuit is disabled and MOEN is low (user manual, chapter 9, break function). |
User manual |
| Clearing OCxREF from an external event | Only output compare mode and PWM mode can clear OCxREF from an external event, and forced mode cannot be used (user manual, chapter 9, clearing the OCREF signal on an external event). |
User manual |
| Condition for OCx fast enable to take effect | OCxFEN fast enable takes effect only when the channel mode is configured as PWM1 or PWM2 (user manual, chapter 9, OCx fast enable). |
User manual |