5.35 DBG Guide

This chapter covers the files of the DBG driver in the N32H49x standard peripheral library and its 8 public functions, which read the device unique IDs and device information and configure debug halting; this SDK has no DBG example project. Read it together with the “Debug support (DBG)” chapter of the user manual for the SWD and JTAG interfaces and the debug control register.

5.35.1 Related files

Relative path	Purpose
`firmware/n32h49x_std_periph_driver/inc/n32h49x_dbg.h`	Defines the debug-halt macros (sleep, stop, standby, and peripheral behavior when the core is halted) and declares the 8 public functions in three sections: ID retrieval, Device information, and Configuration
`firmware/n32h49x_std_periph_driver/src/n32h49x_dbg.c`	Implements the 8 functions: byte-wise ID reads from three base addresses, revision, device number, and FLASH and SRAM size decoding, and read-modify-writes of the debug control register
`firmware/CMSIS/device/n32h49x.h`	Defines the UCID, UID, and DBGMCU_ID base addresses, the `DBG` register structure pointer, and the control-register bit definitions

5.35.2 API reference

The following 8 public functions are listed in the declaration order of n32h49x_dbg.h in 3 groups; each entry gives a summary and the original comment above the function in n32h49x_dbg.c.

ID retrieval

GetUCID, GetUID, GetDBGMCU_ID

Device information

DBG_GetRevNum, DBG_GetDevNum, DBG_GetFlashSize, DBG_GetSramSize

Configuration

DBG_ConfigPeriph

void GetUCID(uint8_t *UCIDbuf)get unique customer id.

Source comment

name    GetUCID.
fun     get unique customer id.
param   UCIDbuf
return  none

void GetUID(uint8_t *UIDbuf)get unique device id.

Source comment

name    GetUID.
fun     get unique device id.
param   UIDbuf
return  none

void GetDBGMCU_ID(uint8_t *DBGMCU_IDbuf)The source comment of this function provides no functional description.

Source comment

@brief  Returns the DBGMCU_ID.
@return DBGMCU_ID

uint32_t DBG_GetRevNum(void)get the revision number.

Source comment

name    DBG_GetRevNum.
fun     get the revision number.
param   none
return  revision number

uint32_t DBG_GetDevNum(void)get the device identifer.

Source comment

name    DBG_GetDevNum.
fun     get the device identifer.
param   none
return  Device identifier

void DBG_ConfigPeriph(uint32_t DBG_Periph, FunctionalState Cmd)Configures the specified peripheral run or stop when the MCU under Debug mode.

Source comment

name    DBG_ConfigPeriph.
fun     Configures the specified peripheral run or stop when the MCU under Debug mode.
param   DBG_Periph :
                - DBG_SLEEP             \* Keep debugger connection during SLEEP mode *\
                - DBG_STOP              \* Keep debugger connection during STOP mode *\
                - DBG_STANDBY           \* Keep debugger connection during STANDBY mode *\
                - DBG_IWDG_STOP         \* IWDG stopped when Core is halted. *\
                - DBG_WWDG_STOP         \* WWDG stopped when Core is halted. *\
                - DBG_I2C1SMBUS_TIMEOUT \* I2C1 SMBUS timeout mode stopped when Core is halted *\
                - DBG_I2C2SMBUS_TIMEOUT \* I2C2 SMBUS timeout mode stopped when Core is halted *\
                - DBG_I2C3SMBUS_TIMEOUT \* I2C3 SMBUS timeout mode stopped when Core is halted *\
                - DBG_I2C4SMBUS_TIMEOUT \* I2C4 SMBUS timeout mode stopped when Core is halted *\
                - DBG_ATIM1_STOP        \* ATIM1 counter stopped when core is halted *\
                - DBG_ATIM2_STOP        \* ATIM2 counter stopped when core is halted *\
                - DBG_ATIM3_STOP        \* ATIM3 counter stopped when core is halted *\
                - DBG_BTIM1_STOP        \* BTIM1 counter stopped when core is halted *\
                - DBG_BTIM2_STOP        \* BTIM2 counter stopped when core is halted *\
                - DBG_GTIM1_STOP        \* GTIM1 counter stopped when core is halted *\
                - DBG_GTIM2_STOP        \* GTIM2 counter stopped when core is halted *\
                - DBG_GTIM3_STOP        \* GTIM3 counter stopped when core is halted *\
                - DBG_GTIM4_STOP        \* GTIM4 counter stopped when core is halted *\
                - DBG_GTIM5_STOP        \* GTIM5 counter stopped when core is halted *\
                - DBG_GTIM6_STOP        \* GTIM6 counter stopped when core is halted *\
                - DBG_GTIM7_STOP        \* GTIM7 counter stopped when core is halted *\
                - DBG_GTIM8_STOP        \* GTIM8 counter stopped when core is halted *\
                - DBG_GTIM9_STOP        \* GTIM9 counter stopped when core is halted *\
                - DBG_GTIM10_STOP       \* GTIM10 counter stopped when core is halted *\
param   Cmd:
          - ENABLE
          - DISABLE
return  none

uint32_t DBG_GetFlashSize(void)Get FLASH size of this chip.

Source comment

name    DBG_GetFlashSize.
fun     Get FLASH size of this chip.
param   none
return  FLASH size in bytes.

uint32_t DBG_GetSramSize(void)Get SRAM size of this chip.

Source comment

name    DBG_GetSramSize.
fun     Get SRAM size of this chip.
param   none
return  SRAM size in bytes.

5.35.3 Demo descriptions

This SDK provides no standalone example project for DBG.

5.35.4 Notes and troubleshooting

Scenario	Check & action	Source
Debug interface switching	The chip uses the JTAG debug interface by default; when both JTAG and SWD are enabled, the 5-wire JTAG interface is used after reset; switching from JTAG to SWD sends JTMS=1 for more than 50 JTCK cycles, then 16 bits of 0xE79E, then JTMS=1 for more than 50 JTCK cycles again; switching back from SWD to JTAG uses 16 bits of 0xE73C with the same other steps.	User manual
Debug pin reuse	JTMS/SWDIO is PA13, JTCK/SWCLK is PA14, JTDI is PA15, JTDO is PB3 or PG15, and NJTRST is PB4; when using JTAG, NJTRST may be left unused and PB4 can serve as a general-purpose GPIO; when using SWD, JTDI, JTDO, and NJTRST can serve as general-purpose GPIO; when debug is not used, all five pins can serve as general-purpose GPIO.	User manual
Debug in low-power modes	Debugging in low-power modes requires the core FCLK and HCLK to stay on; DBG_SLEEP mode configures the DBG_CTRL.SLEEP bit to supply HCLK with the same system clock as FCLK; DBG_STOP and DBG_STANDBY modes configure the DBG_CTRL.STOP and DBG_CTRL.STDBY bits to start the internal RC oscillator for HCLK and FCLK.	User manual
Peripheral debug	Setting the corresponding peripheral control bits in DBG_CTRL to 1 puts the peripheral into debug state after the core stops; timer counters stop and enter the debug state; the I2C SMBUS keeps its state; the WWDG and IWDG counters stop and enter the debug state.	User manual
Register access	DBG peripheral registers must be accessed as 32-bit words, with the register base address 0xE0042000; the POR reset value of DBG_CTRL is 0x00000000, and a system reset does not reset this register.	User manual