AI FAE Platform5.20 TIM Guide
This chapter describes the file composition and the 154 public functions of the TIM driver in the N32G41x standard peripheral library, covering the time base, output compare, input capture, complementary output and break/dead-time, encoder, slave/master mode and synchronisation, DMA, and interrupt and flag management of the advanced-control timers ATIM1/ATIM2, the general-purpose timers GTIM1 and GTIM2, the general-purpose control timers GTIM3/GTIM4 and the basic timers BTIM1/BTIM2; the 18 examples under projects/n32g41x_EVAL/examples/TIM/ demonstrate PWM output and input, input capture, one-pulse and various synchronisation and DMA uses. Read the register definitions and mode restrictions of each timer together with the “Advanced-control timers (ATIM1/ATIM2)”, “General-purpose timer (GTIM1)”, “General-purpose timer (GTIM2)”, “General-purpose control timers (GTIM3/GTIM4)” and “Basic timers (BTIM1/BTIM2)” chapters of the user manual, and take the errata sheet as the authority on known chip issues.
5.20.1 Related files
| Relative path | Purpose |
|---|---|
firmware/n32g41x_std_periph_driver/inc/n32g41x_tim.h |
Defines the five initialisation structures for the time base, output compare, input capture, BKDT and filtering together with the mode and channel macros, and declares 154 public functions in ten functional sections |
firmware/n32g41x_std_periph_driver/src/n32g41x_tim.c |
Implements those 154 functions: read and write accesses to registers such as CTRL1, CTRL2, STS, CCMODx, CCEN and CCDATx, covering time base and prescaler setup, output compare and PWM, input capture and filtering, break and dead time, encoder interface, trigger and synchronisation, DMA requests, and interrupt and flag management |
projects/n32g41x_EVAL/examples/TIM/ |
Contains 18 examples: 6Steps, ATIM1_Synchro, Cascade_Synchro, ComplementarySignals, DMA, DMABurst, ExtTrigger_Synchro, InputCapture, OCActive, OCInactive, OCToggle, OnePulse, Parallel_Synchro, PWM_Input, PWM_Output, TimeBasic6_BTIM_wakeup, TimeBasic_cc, TimeBasic_update |
projects/n32g41x_EVAL/examples/TIM/PWM_Output/ |
The example project demonstrating the main function, with src/main.c, src/n32g41x_it.c, inc/main.h, inc/n32g41x_it.h, readme.txt and the MDK-ARM/ and EWARM/ build projects |
firmware/CMSIS/device/n32g41x.h |
Defines the TIM_Module register structure, the base pointers ATIM1/ATIM2/GTIM1 to GTIM4/BTIM1/BTIM2 and the register map of each timer |
5.20.2 API reference
The following 154 public functions are listed in the declaration order of n32g41x_tim.h in 10 groups; each entry gives a summary and the original comment above the function in n32g41x_tim.c.
Reset and initialisation
TIM_DeInit, TIM_InitTimeBase, TIM_InitTimBaseStruct, TIM_InitOcStruct, TIM_InitIcStruct, TIM_InitBkdtStruct, TIM_Enable
Time base configuration
TIM_ConfigPrescaler, TIM_ConfigCntMode, TIM_ConfigArPreload, TIM_SetCnt, TIM_SetAutoReload, TIM_GetCnt, TIM_GetPrescaler, TIM_GetAutoReload, TIM_SetClkDiv, TIM_ConfigUpdateEvt, TIM_ConfigUpdateRequestIntSrc, TIM_SelectOnePulseMode, TIM_GenerateEvent
Output compare
TIM_InitOc1, TIM_InitOc2, TIM_InitOc3, TIM_InitOc4, TIM_InitOc5, TIM_InitOc6, TIM_SelectOcMode, TIM_ConfigForcedOc1, TIM_ConfigForcedOc2, TIM_ConfigForcedOc3, TIM_ConfigForcedOc4, TIM_ConfigForcedOc5, TIM_ConfigForcedOc6, TIM_ConfigOc1Preload, TIM_ConfigOc2Preload, TIM_ConfigOc3Preload, TIM_ConfigOc4Preload, TIM_ConfigOc5Preload, TIM_ConfigOc6Preload, TIM_ConfigOc7Preload, TIM_ConfigOc8Preload, TIM_ConfigOc9Preload, TIM_ConfigOc1Fast, TIM_ConfigOc2Fast, TIM_ConfigOc3Fast, TIM_ConfigOc4Fast, TIM_ConfigOc5Fast, TIM_ConfigOc6Fast, TIM_ClrOc1Ref, TIM_ClrOc2Ref, TIM_ClrOc3Ref, TIM_ClrOc4Ref, TIM_ClrOc5Ref, TIM_ClrOc6Ref, TIM_ClrOcRefInputSource, TIM_ConfigOc1Polarity, TIM_ConfigOc1NPolarity, TIM_ConfigOc2Polarity, TIM_ConfigOc2NPolarity, TIM_ConfigOc3Polarity, TIM_ConfigOc3NPolarity, TIM_ConfigOc4Polarity, TIM_ConfigOc4NPolarity, TIM_ConfigOc5Polarity, TIM_ConfigOc6Polarity, TIM_EnableCapCmpCh, TIM_EnableCapCmpChN, TIM_SetCmp1, TIM_SetCmp2, TIM_SetCmp3, TIM_SetCmp4, TIM_SetCmp5, TIM_SetCmp6, TIM_SetCmp7, TIM_SetCmp8, TIM_SetCmp9, TIM_SetCmp1D, TIM_SetCmp2D, TIM_SetCmp3D, TIM_SetCmp4D, TIM_AsymmetricEnable, TIM_SelectCenterAlignTrig, TIM_OCxRefTriggerADC
Input capture
TIM_ICInit, TIM_ConfigPwmIc, ConfigTI1, ConfigTI2, ConfigTI3, ConfigTI4, TIM_SetInCap1Prescaler, TIM_SetInCap2Prescaler, TIM_SetInCap3Prescaler, TIM_SetInCap4Prescaler, TIM_GetCap1, TIM_GetCap2, TIM_GetCap3, TIM_GetCap4, TIM_GetCap5, TIM_GetCap6, TIM_GetCap7, TIM_GetCap8, TIM_GetCap9, TIM_GetCap1D, TIM_GetCap2D, TIM_GetCap3D, TIM_GetCap4D
Input capture filtering
TIM_IC1FiltConfig, TIM_IC2FiltConfig, TIM_IC3FiltConfig, TIM_IC4FiltConfig, TIM_IC1FiltEnable, TIM_IC2FiltEnable, TIM_IC3FiltEnable, TIM_IC4FiltEnable, TIM_GetFiltStatus
Complementary output and break/dead-time
TIM_EnableCtrlPwmOutputs, TIM_ConfigBkdt, TIM_BreakFiltConfig, TIM_BreakFiltEnable, TIM_BreakInputSourceEnable, TIM_BidirectionDisarm, TIM_BidirectionRearm, TIM_SelectComEvt, TIM_SelectCapCmpDmaSrc, TIM_EnableCapCmpPreloadControl, TIM_GetCCENStatus
Encoder interface
TIM_ConfigEncoderInterface, TIM_ConfigEncoderInterface2, TIM_TrgiLoadLvrToCNTEnable, TIM_GetLVR, TIM_CH3LoadLvrToCNTEnable, TIM_CH3LoadLvrToCNTPolarity, TIM_GetENCDAT, TIM_GetENCDATSign
Slave/master mode and synchronisation
TIM_ConfigInternalClk, TIM_SelectInputTrig, TIM_ConfigInternalTrigToExt, TIM_ConfigExtTrigAsClk, TIM_ConfigExtClkMode1, TIM_ConfigExtClkMode2, TIM_ConfigExtTrig, TIM_SelectETRInputSource, TIM_SelectOutputTrig, TIM_SelectOutputTrig2, TIM_SelectSlaveMode, TIM_SelectMasterSlaveMode, TIM_SelectHallSensor
DMA
TIM_ConfigDma, TIM_EnableDma
Interrupt and flag management
TIM_ConfigInt, TIM_GetFlagStatus, TIM_ClearFlag, TIM_GetIntStatus, TIM_ClrIntPendingBit
void TIM_DeInit(const TIM_Module *TIMx)Deinitializes the TIMx registers.
name TIM_DeInit
fun Deinitializes the TIMx registers.
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
- GTIM1
- GTIM2
- GTIM3
- GTIM4
- BTIM1
- BTIM2
return none
void TIM_InitTimeBase(TIM_Module *TIMx, const TIM_TimeBaseInitType *TIM_TimeBaseInitStruct)Initializes the TIMx time base unit.
name TIM_InitTimeBase
fun Initializes the TIMx time base unit.
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
- GTIM1
- GTIM2
- GTIM3
- GTIM4
- BTIM1
- BTIM2
param TIM_TimeBaseInitStruct: refer to the definition of TIM_TimeBaseInitType
- Prescaler
* 0x0000 ~ 0xFFFF
- CounterMode
* TIM_CNT_MODE_UP
* TIM_CNT_MODE_DOWN
* TIM_CNT_MODE_CENTER_ALIGN1
* TIM_CNT_MODE_CENTER_ALIGN2
* TIM_CNT_MODE_CENTER_ALIGN3
- Period
* 0x00000000 ~ 0xFFFFFFFF
- ClkDiv
* TIM_CLK_DIV1
* TIM_CLK_DIV2
* TIM_CLK_DIV4
- RepetCnt
* 0x00 ~ 0xFF
- CapCh1Sel
* TIM_CAPCH1SEL_0
* TIM_CAPCH1SEL_1
* TIM_CAPCH1SEL_2
* TIM_CAPCH1SEL_3
* TIM_CAPCH1SEL_4
* TIM_CAPCH1SEL_5
* TIM_CAPCH1SEL_6
- CapCh2Sel
* TIM_CAPCH2SEL_0
* TIM_CAPCH2SEL_1
* TIM_CAPCH2SEL_2
- CapCh3Sel
* TIM_CAPCH3SEL_0
* TIM_CAPCH3SEL_1
* TIM_CAPCH3SEL_2
- CapCh4Sel
* TIM_CAPCH4SEL_0
* TIM_CAPCH4SEL_1
* TIM_CAPCH4SEL_2
- EtrOrClr
* TIM_ETRSEL
* TIM_CLRSEL
- CapEtrClrSel
* TIM_CAPETRSEL_0
* TIM_CAPETRSEL_1
* TIM_CAPETRSEL_2
* TIM_CAPETRSEL_3
* TIM_CAPETRSEL_4
* TIM_CAPETRSEL_5
* TIM_OCCLRSEL_0
* TIM_OCCLRSEL_1
* TIM_OCCLRSEL_2
return none
note GTIM1 is a 32-bit timer, while the others are 16-bit timers.
void TIM_InitTimBaseStruct(TIM_TimeBaseInitType *TIM_TimeBaseInitStruct)Fills each TIM_TimeBaseInitStruct member with its default value.
name TIM_InitTimBaseStruct
fun Fills each TIM_TimeBaseInitStruct member with its default value.
param TIM_TimeBaseInitStruct: refer to the definition of TIM_TimeBaseInitType
- Prescaler
* 0x0000 ~ 0xFFFF
- CounterMode
* TIM_CNT_MODE_UP
* TIM_CNT_MODE_DOWN
* TIM_CNT_MODE_CENTER_ALIGN1
* TIM_CNT_MODE_CENTER_ALIGN2
* TIM_CNT_MODE_CENTER_ALIGN3
- Period
* 0x00000000 ~ 0xFFFFFFFF
- ClkDiv
* TIM_CLK_DIV1
* TIM_CLK_DIV2
* TIM_CLK_DIV4
- RepetCnt
* 0x00 ~ 0xFF
- CapCh1Sel
* TIM_CAPCH1SEL_0
* TIM_CAPCH1SEL_1
* TIM_CAPCH1SEL_2
* TIM_CAPCH1SEL_3
* TIM_CAPCH1SEL_4
* TIM_CAPCH1SEL_5
* TIM_CAPCH1SEL_6
- CapCh2Sel
* TIM_CAPCH2SEL_0
* TIM_CAPCH2SEL_1
* TIM_CAPCH2SEL_2
- CapCh3Sel
* TIM_CAPCH3SEL_0
* TIM_CAPCH3SEL_1
* TIM_CAPCH3SEL_2
- CapCh4Sel
* TIM_CAPCH4SEL_0
* TIM_CAPCH4SEL_1
* TIM_CAPCH4SEL_2
- EtrOrClr
* TIM_ETRSEL
* TIM_CLRSEL
- CapEtrClrSel
* TIM_CAPETRSEL_0
* TIM_CAPETRSEL_1
* TIM_CAPETRSEL_2
* TIM_CAPETRSEL_3
* TIM_CAPETRSEL_4
* TIM_CAPETRSEL_5
* TIM_OCCLRSEL_0
* TIM_OCCLRSEL_1
* TIM_OCCLRSEL_2
return none
void TIM_InitOcStruct(OCInitType *TIM_OCInitStruct)Fills each TIM_OCInitStruct member with its default value.
name TIM_InitOcStruct
fun Fills each TIM_OCInitStruct member with its default value.
param TIM_OCInitStruct: refer to the definition of OCInitType
- OCMode
* TIM_OCMODE_TIMING
* TIM_OCMODE_ACTIVE
* TIM_OCMODE_INACTIVE
* TIM_OCMODE_TOGGLE
* TIM_FORCED_ACTION_INACTIVE
* TIM_FORCED_ACTION_ACTIVE
* TIM_OCMODE_PWM1
* TIM_OCMODE_PWM2
* TIM_OCMODE_OPMOD_RETRIG1
* TIM_OCMODE_OPMOD_RETRIG2
* TIM_OCMODE_COMBI_PWM1
* TIM_OCMODE_COMBI_PWM2
- OutputState
* TIM_OUTPUT_STATE_DISABLE
* TIM_OUTPUT_STATE_ENABLE
- OutputNState
* TIM_OUTPUT_NSTATE_DISABLE
* TIM_OUTPUT_NSTATE_ENABLE
- Pulse
* 0x00000000 ~ 0xFFFFFFFF
- OCPolarity
* TIM_OC_POLARITY_HIGH
* TIM_OC_POLARITY_LOW
- OCNPolarity
* TIM_OCN_POLARITY_HIGH
* TIM_OCN_POLARITY_LOW
- OCIdleState
* TIM_OC_IDLE_STATE_SET
* TIM_OC_IDLE_STATE_RESET
- OCNIdleState
* TIM_OCN_IDLE_STATE_SET
* TIM_OCN_IDLE_STATE_RESET
return none
void TIM_InitIcStruct(TIM_ICInitType *TIM_ICInitStruct)Fills each TIM_ICInitStruct member with its default value.
name TIM_InitIcStruct
fun Fills each TIM_ICInitStruct member with its default value.
param TIM_ICInitStruct: refer to the definition of TIM_ICInitType
- Channel
* TIM_CH_1
* TIM_CH_2
* TIM_CH_3
* TIM_CH_4
- ICPolarity
* TIM_IC_POLARITY_RISING
* TIM_IC_POLARITY_FALLING
- ICSelection
* TIM_IC_SELECTION_DIRECTTI
* TIM_IC_SELECTION_INDIRECTTI
* TIM_IC_SELECTION_TRC
- ICPrescaler
* TIM_IC_PSC_DIV1
* TIM_IC_PSC_DIV2
* TIM_IC_PSC_DIV4
* TIM_IC_PSC_DIV8
- ICFilter
* ICFilter can be a number between 0x0 and 0xF
return none
void TIM_InitBkdtStruct(TIM_BDTRInitType *TIM_BDTRInitStruct)Fills each TIM_BDTRInitStruct member with its default value.
name TIM_InitBkdtStruct
fun Fills each TIM_BDTRInitStruct member with its default value.
param TIM_BDTRInitStruct: refer to the definition of TIM_BDTRInitType
- OSSRState
* TIM_OSSR_STATE_ENABLE
* TIM_OSSR_STATE_DISABLE
- OSSIState
* TIM_OSSI_STATE_ENABLE
* TIM_OSSI_STATE_DISABLE
- LOCKLevel
* TIM_LOCK_LEVEL_OFF
* TIM_LOCK_LEVEL_1
* TIM_LOCK_LEVEL_2
* TIM_LOCK_LEVEL_3
- DeadTime
* DeadTime can be a number between 0x00 and 0xFF
- Break
* TIM_BREAK_IN_ENABLE
* TIM_BREAK_IN_DISABLE
- BreakPolarity
* TIM_BREAK_POLARITY_LOW
* TIM_BREAK_POLARITY_HIGH
- Bidirection
* TIM_BREAK_BID_ENABLE
* TIM_BREAK_BID_DISABLE
- AutomaticOutput
* TIM_AUTO_OUTPUT_ENABLE
* TIM_AUTO_OUTPUT_DISABLE
return none
void TIM_Enable(TIM_Module *TIMx, FunctionalState Cmd)Enables or disables the specified TIM peripheral.
name TIM_Enable
fun Enables or disables the specified TIM peripheral.
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
- GTIM1
- GTIM2
- GTIM3
- GTIM4
- BTIM1
- BTIM2
param Cmd :
- ENABLE
- DISABLE
return none
void TIM_ConfigPrescaler(TIM_Module *TIMx, uint32_t Prescaler, uint32_t TIM_PSCReloadMode)Configures the TIMx Prescaler.
name TIM_ConfigPrescaler
fun Configures the TIMx Prescaler.
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
- GTIM1
- GTIM2
- GTIM3
- GTIM4
- BTIM1
- BTIM2
param Prescaler:
- 0x0000 ~ 0xFFFF
param TIM_PSCReloadMode
- TIM_PSC_RELOAD_MODE_UPDATE
- TIM_PSC_RELOAD_MODE_IMMEDIATE
return none
void TIM_ConfigCntMode(TIM_Module *TIMx, uint32_t CntMode)Specifies the TIMx Counter Mode to be used.
name TIM_ConfigCntMode
fun Specifies the TIMx Counter Mode to be used.
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
- GTIM1
- GTIM2
- GTIM3
- GTIM4
- BTIM1
- BTIM2
param CntMode
- TIM_CNT_MODE_UP
- TIM_CNT_MODE_DOWN
- TIM_CNT_MODE_CENTER_ALIGN1
- TIM_CNT_MODE_CENTER_ALIGN2
- TIM_CNT_MODE_CENTER_ALIGN3
return none
void TIM_ConfigArPreload(TIM_Module *TIMx, FunctionalState Cmd)Enables or disables TIMx peripheral Preload register on AR.
name TIM_ConfigArPreload
fun Enables or disables TIMx peripheral Preload register on AR.
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
- GTIM1
- GTIM2
- GTIM3
- GTIM4
- BTIM1
- BTIM2
param Cmd
- ENABLE
- DISABLE
return none
void TIM_SetCnt(TIM_Module *TIMx, uint32_t Counter)Sets the TIMx Counter Register value
name TIM_SetCnt
fun Sets the TIMx Counter Register value
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
- GTIM1
- GTIM2
- GTIM3
- GTIM4
- BTIM1
- BTIM2
param Counter
- Counter can be a number between 0x00000000 and 0xFFFFFFFF
return none
void TIM_SetAutoReload(TIM_Module *TIMx, uint32_t Autoreload)Sets the TIMx Autoreload Register value
name TIM_SetAutoReload
fun Sets the TIMx Autoreload Register value
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
- GTIM1
- GTIM2
- GTIM3
- GTIM4
- BTIM1
- BTIM2
param Autoreload
- Autoreload can be a number between 0x00000000 and 0xFFFFFFFF
return none
uint32_t TIM_GetCnt(const TIM_Module *TIMx)Gets the TIMx Counter value.
name TIM_GetCnt
fun Gets the TIMx Counter value.
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
- GTIM1
- GTIM2
- GTIM3
- GTIM4
- BTIM1
- BTIM2
return Counter Register value.
uint16_t TIM_GetPrescaler(const TIM_Module *TIMx)Gets the TIMx Prescaler value.
name TIM_GetPrescaler
fun Gets the TIMx Prescaler value.
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
- GTIM1
- GTIM2
- GTIM3
- GTIM4
- BTIM1
- BTIM2
return Prescaler Register value.
uint32_t TIM_GetAutoReload(const TIM_Module *TIMx)Gets the TIMx AR value.
name TIM_GetAutoReload
fun Gets the TIMx AR value.
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
- GTIM1
- GTIM2
- GTIM3
- GTIM4
- BTIM1
- BTIM2
return AR Register value.
void TIM_SetClkDiv(TIM_Module *TIMx, uint32_t TIM_CKD)Sets the TIMx Clock Division value.
name TIM_SetClkDiv
fun Sets the TIMx Clock Division value.
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
- GTIM1
- GTIM2
- GTIM3
- GTIM4
param TIM_CKD:
- TIM_CLK_DIV1
- TIM_CLK_DIV2
- TIM_CLK_DIV4
return none
void TIM_ConfigUpdateEvt(TIM_Module *TIMx, FunctionalState Cmd)Enables or Disables the TIMx Update event.
name TIM_ConfigUpdateEvt
fun Enables or Disables the TIMx Update event.
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
- GTIM1
- GTIM2
- GTIM3
- GTIM4
- BTIM1
- BTIM2
param Cmd
- ENABLE
- DISABLE
return none
void TIM_ConfigUpdateRequestIntSrc(TIM_Module *TIMx, uint32_t TIM_UpdateSource)Configures the TIMx Update Request Interrupt source.
name TIM_ConfigUpdateRequestIntSrc
fun Configures the TIMx Update Request Interrupt source.
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
- GTIM1
- GTIM2
- GTIM3
- GTIM4
- BTIM1
- BTIM2
param TIM_UpdateSource
- TIM_UPDATE_SRC_GLOBAL
- TIM_UPDATE_SRC_REGULAR
return none
Use note: The implementation sets or clears the UPRS bit of TIMx->CTRL1 according to TIM_UpdateSource; passing TIM_UPDATE_SRC_GLOBAL clears it.
void TIM_SelectOnePulseMode(TIM_Module *TIMx, uint32_t TIM_OPMode)Selects the TIMx’s One Pulse Mode.
name TIM_SelectOnePulseMode
fun Selects the TIMx's One Pulse Mode.
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
- GTIM1
- GTIM2
- GTIM3
- GTIM4
param TIM_OPMode
- TIM_OPMODE_SINGLE
- TIM_OPMODE_REPET
return none
void TIM_GenerateEvent(TIM_Module *TIMx, uint32_t TIM_EventSource)Configures the TIMx event to be generate by software.
name TIM_GenerateEvent
fun Configures the TIMx event to be generate by software.
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
- GTIM1
- GTIM2
- GTIM3
- GTIM4
- BTIM1
- BTIM2
param TIM_EventSource:
- TIM_EVT_SRC_CC1
- TIM_EVT_SRC_CC2
- TIM_EVT_SRC_CC3
- TIM_EVT_SRC_CC4
- TIM_EVT_SRC_UPDATE
- TIM_EVT_SRC_COM
- TIM_EVT_SRC_TRIG
- TIM_EVT_SRC_BREAK
return none
void TIM_InitOc1(TIM_Module *TIMx, const OCInitType *TIM_OCInitStruct)Initializes the TIMx Channel 1.
name TIM_InitOc1
fun Initializes the TIMx Channel 1.
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
- GTIM1
- GTIM2
- GTIM3
- GTIM4
param TIM_OCInitStruct: refer to the definition of OCInitType
- OCMode
* TIM_OCMODE_TIMING
* TIM_OCMODE_ACTIVE
* TIM_OCMODE_INACTIVE
* TIM_OCMODE_TOGGLE
* TIM_FORCED_ACTION_INACTIVE
* TIM_FORCED_ACTION_ACTIVE
* TIM_OCMODE_PWM1
* TIM_OCMODE_PWM2
* TIM_OCMODE_OPMOD_RETRIG1
* TIM_OCMODE_OPMOD_RETRIG2
* TIM_OCMODE_COMBI_PWM1
* TIM_OCMODE_COMBI_PWM2
- OutputState
* TIM_OUTPUT_STATE_DISABLE
* TIM_OUTPUT_STATE_ENABLE
- OutputNState
* TIM_OUTPUT_NSTATE_DISABLE
* TIM_OUTPUT_NSTATE_ENABLE
- Pulse
* 0x00000000 ~ 0xFFFFFFFF
- OCPolarity
* TIM_OC_POLARITY_HIGH
* TIM_OC_POLARITY_LOW
- OCNPolarity
* TIM_OCN_POLARITY_HIGH
* TIM_OCN_POLARITY_LOW
- OCIdleState
* TIM_OC_IDLE_STATE_SET
* TIM_OC_IDLE_STATE_RESET
- OCNIdleState
* TIM_OCN_IDLE_STATE_SET
* TIM_OCN_IDLE_STATE_RESET
return none
void TIM_InitOc2(TIM_Module *TIMx, const OCInitType *TIM_OCInitStruct)Initializes the TIMx Channel 2.
name TIM_InitOc2
fun Initializes the TIMx Channel 2.
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
- GTIM1
- GTIM2
- GTIM3
- GTIM4
param TIM_OCInitStruct: refer to the definition of OCInitType
- OCMode
* TIM_OCMODE_TIMING
* TIM_OCMODE_ACTIVE
* TIM_OCMODE_INACTIVE
* TIM_OCMODE_TOGGLE
* TIM_FORCED_ACTION_INACTIVE
* TIM_FORCED_ACTION_ACTIVE
* TIM_OCMODE_PWM1
* TIM_OCMODE_PWM2
* TIM_OCMODE_OPMOD_RETRIG1
* TIM_OCMODE_OPMOD_RETRIG2
* TIM_OCMODE_COMBI_PWM1
* TIM_OCMODE_COMBI_PWM2
- OutputState
* TIM_OUTPUT_STATE_DISABLE
* TIM_OUTPUT_STATE_ENABLE
- OutputNState
* TIM_OUTPUT_NSTATE_DISABLE
* TIM_OUTPUT_NSTATE_ENABLE
- Pulse
* 0x00000000 ~ 0xFFFFFFFF
- OCPolarity
* TIM_OC_POLARITY_HIGH
* TIM_OC_POLARITY_LOW
- OCNPolarity
* TIM_OCN_POLARITY_HIGH
* TIM_OCN_POLARITY_LOW
- OCIdleState
* TIM_OC_IDLE_STATE_SET
* TIM_OC_IDLE_STATE_RESET
- OCNIdleState
* TIM_OCN_IDLE_STATE_SET
* TIM_OCN_IDLE_STATE_RESET
return none
void TIM_InitOc3(TIM_Module *TIMx, const OCInitType *TIM_OCInitStruct)Initializes the TIMx Channel 3.
name TIM_InitOc3
fun Initializes the TIMx Channel 3.
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
- GTIM1
- GTIM2
- GTIM3
- GTIM4
param TIM_OCInitStruct: refer to the definition of OCInitType
- OCMode
* TIM_OCMODE_TIMING
* TIM_OCMODE_ACTIVE
* TIM_OCMODE_INACTIVE
* TIM_OCMODE_TOGGLE
* TIM_FORCED_ACTION_INACTIVE
* TIM_FORCED_ACTION_ACTIVE
* TIM_OCMODE_PWM1
* TIM_OCMODE_PWM2
* TIM_OCMODE_OPMOD_RETRIG1
* TIM_OCMODE_OPMOD_RETRIG2
* TIM_OCMODE_COMBI_PWM1
* TIM_OCMODE_COMBI_PWM2
- OutputState
* TIM_OUTPUT_STATE_DISABLE
* TIM_OUTPUT_STATE_ENABLE
- OutputNState
* TIM_OUTPUT_NSTATE_DISABLE
* TIM_OUTPUT_NSTATE_ENABLE
- Pulse
* 0x00000000 ~ 0xFFFFFFFF
- OCPolarity
* TIM_OC_POLARITY_HIGH
* TIM_OC_POLARITY_LOW
- OCNPolarity
* TIM_OCN_POLARITY_HIGH
* TIM_OCN_POLARITY_LOW
- OCIdleState
* TIM_OC_IDLE_STATE_SET
* TIM_OC_IDLE_STATE_RESET
- OCNIdleState
* TIM_OCN_IDLE_STATE_SET
* TIM_OCN_IDLE_STATE_RESET
return none
void TIM_InitOc4(TIM_Module *TIMx, const OCInitType *TIM_OCInitStruct)Initializes the TIMx Channel 4.
name TIM_InitOc4
fun Initializes the TIMx Channel 4.
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
- GTIM1
- GTIM2
- GTIM3
- GTIM4
param TIM_OCInitStruct: refer to the definition of OCInitType
- OCMode
* TIM_OCMODE_TIMING
* TIM_OCMODE_ACTIVE
* TIM_OCMODE_INACTIVE
* TIM_OCMODE_TOGGLE
* TIM_FORCED_ACTION_INACTIVE
* TIM_FORCED_ACTION_ACTIVE
* TIM_OCMODE_PWM1
* TIM_OCMODE_PWM2
* TIM_OCMODE_OPMOD_RETRIG1
* TIM_OCMODE_OPMOD_RETRIG2
* TIM_OCMODE_COMBI_PWM1
* TIM_OCMODE_COMBI_PWM2
- OutputState
* TIM_OUTPUT_STATE_DISABLE
* TIM_OUTPUT_STATE_ENABLE
- OutputNState
* TIM_OUTPUT_NSTATE_DISABLE
* TIM_OUTPUT_NSTATE_ENABLE
- Pulse
* 0x00000000 ~ 0xFFFFFFFF
- OCPolarity
* TIM_OC_POLARITY_HIGH
* TIM_OC_POLARITY_LOW
- OCNPolarity
* TIM_OCN_POLARITY_HIGH
* TIM_OCN_POLARITY_LOW
- OCIdleState
* TIM_OC_IDLE_STATE_SET
* TIM_OC_IDLE_STATE_RESET
- OCNIdleState
* TIM_OCN_IDLE_STATE_SET
* TIM_OCN_IDLE_STATE_RESET
return none
void TIM_InitOc5(TIM_Module *TIMx, const OCInitType *TIM_OCInitStruct)Initializes the TIMx Channel 5.
name TIM_InitOc5
fun Initializes the TIMx Channel 5.
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
param TIM_OCInitStruct: refer to the definition of OCInitType
- OCMode
* TIM_OCMODE_TIMING
* TIM_OCMODE_ACTIVE
* TIM_OCMODE_INACTIVE
* TIM_OCMODE_TOGGLE
* TIM_FORCED_ACTION_INACTIVE
* TIM_FORCED_ACTION_ACTIVE
* TIM_OCMODE_PWM1
* TIM_OCMODE_PWM2
- OutputState
* TIM_OUTPUT_STATE_DISABLE
* TIM_OUTPUT_STATE_ENABLE
- Pulse
* 0x0000 ~ 0xFFFF
- OCPolarity
* TIM_OC_POLARITY_HIGH
* TIM_OC_POLARITY_LOW
- OCIdleState none
return none
void TIM_InitOc6(TIM_Module *TIMx, const OCInitType *TIM_OCInitStruct)Initializes the TIMx Channel 6.
name TIM_InitOc6
fun Initializes the TIMx Channel 6.
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
param TIM_OCInitStruct: refer to the definition of OCInitType
- OCMode
* TIM_OCMODE_TIMING
* TIM_OCMODE_ACTIVE
* TIM_OCMODE_INACTIVE
* TIM_OCMODE_TOGGLE
* TIM_FORCED_ACTION_INACTIVE
* TIM_FORCED_ACTION_ACTIVE
* TIM_OCMODE_PWM1
* TIM_OCMODE_PWM2
- OutputState
* TIM_OUTPUT_STATE_DISABLE
* TIM_OUTPUT_STATE_ENABLE
- Pulse
* 0x0000 ~ 0xFFFF
- OCPolarity
* TIM_OC_POLARITY_HIGH
* TIM_OC_POLARITY_LOW
return none
void TIM_SelectOcMode(TIM_Module *TIMx, uint32_t Channel, uint32_t OcMode)Selects the TIM Output Compare Mode.
name TIM_SelectOcMode
fun Selects the TIM Output Compare Mode.
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
- GTIM1
- GTIM2
- GTIM3
- GTIM4
param Channel
- TIM_CH_1
- TIM_CH_2
- TIM_CH_3
- TIM_CH_4
- TIM_CH_5
- TIM_CH_6
param OcMode
- TIM_OCMODE_TIMING
- TIM_OCMODE_ACTIVE
- TIM_OCMODE_INACTIVE
- TIM_OCMODE_TOGGLE
- TIM_OCMODE_PWM1
- TIM_OCMODE_PWM2
- TIM_FORCED_ACTION_ACTIVE
- TIM_FORCED_ACTION_INACTIVE
- TIM_OCMODE_OPMOD_RETRIG1
- TIM_OCMODE_OPMOD_RETRIG2
- TIM_OCMODE_COMBI_PWM1
- TIM_OCMODE_COMBI_PWM2
return none
void TIM_ConfigForcedOc1(TIM_Module *TIMx, uint32_t TIM_ForcedAction)Forces the TIMx output 1 waveform to active or inactive level.
name TIM_ConfigForcedOc1
fun Forces the TIMx output 1 waveform to active or inactive level.
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
- GTIM1
- GTIM2
- GTIM3
- GTIM4
param TIM_ForcedAction
- TIM_FORCED_ACTION_ACTIVE
- TIM_FORCED_ACTION_INACTIVE
return none
void TIM_ConfigForcedOc2(TIM_Module *TIMx, uint32_t TIM_ForcedAction)Forces the TIMx output 2 waveform to active or inactive level.
name TIM_ConfigForcedOc2
fun Forces the TIMx output 2 waveform to active or inactive level.
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
- GTIM1
- GTIM2
- GTIM3
- GTIM4
param TIM_ForcedAction
- TIM_FORCED_ACTION_ACTIVE
- TIM_FORCED_ACTION_INACTIVE
return none
void TIM_ConfigForcedOc3(TIM_Module *TIMx, uint32_t TIM_ForcedAction)Forces the TIMx output 3 waveform to active or inactive level.
name TIM_ConfigForcedOc3
fun Forces the TIMx output 3 waveform to active or inactive level.
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
- GTIM1
- GTIM2
- GTIM3
- GTIM4
param TIM_ForcedAction
- TIM_FORCED_ACTION_ACTIVE
- TIM_FORCED_ACTION_INACTIVE
return none
void TIM_ConfigForcedOc4(TIM_Module *TIMx, uint32_t TIM_ForcedAction)Forces the TIMx output 4 waveform to active or inactive level.
name TIM_ConfigForcedOc4
fun Forces the TIMx output 4 waveform to active or inactive level.
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
- GTIM1
- GTIM2
- GTIM3
- GTIM4
param TIM_ForcedAction
- TIM_FORCED_ACTION_ACTIVE
- TIM_FORCED_ACTION_INACTIVE
return none
void TIM_ConfigForcedOc5(TIM_Module *TIMx, uint32_t TIM_ForcedAction)Forces the TIMx output 5 waveform to active or inactive level.
name TIM_ConfigForcedOc5
fun Forces the TIMx output 5 waveform to active or inactive level.
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
param TIM_ForcedAction
- TIM_FORCED_ACTION_ACTIVE
- TIM_FORCED_ACTION_INACTIVE
return none
void TIM_ConfigForcedOc6(TIM_Module *TIMx, uint32_t TIM_ForcedAction)Forces the TIMx output 6 waveform to active or inactive level.
name TIM_ConfigForcedOc6
fun Forces the TIMx output 6 waveform to active or inactive level.
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
param TIM_ForcedAction
- TIM_FORCED_ACTION_ACTIVE
- TIM_FORCED_ACTION_INACTIVE
return none
void TIM_ConfigOc1Preload(TIM_Module *TIMx, uint32_t TIM_OCPreload)Enables or disables the TIMx peripheral Preload register on CCDAT1.
name TIM_ConfigOc1Preload
fun Enables or disables the TIMx peripheral Preload register on CCDAT1.
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
- GTIM1
- GTIM2
- GTIM3
- GTIM4
param TIM_OCPreload
- TIM_OC_PRE_LOAD_ENABLE
- TIM_OC_PRE_LOAD_DISABLE
return none
void TIM_ConfigOc2Preload(TIM_Module *TIMx, uint32_t TIM_OCPreload)Enables or disables the TIMx peripheral Preload register on CCDAT2.
name TIM_ConfigOc2Preload
fun Enables or disables the TIMx peripheral Preload register on CCDAT2.
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
- GTIM1
- GTIM2
- GTIM3
- GTIM4
param TIM_OCPreload
- TIM_OC_PRE_LOAD_ENABLE
- TIM_OC_PRE_LOAD_DISABLE
return none
void TIM_ConfigOc3Preload(TIM_Module *TIMx, uint32_t TIM_OCPreload)Enables or disables the TIMx peripheral Preload register on CCDAT3.
name TIM_ConfigOc3Preload
fun Enables or disables the TIMx peripheral Preload register on CCDAT3.
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
- GTIM1
- GTIM2
- GTIM3
- GTIM4
param TIM_OCPreload
- TIM_OC_PRE_LOAD_ENABLE
- TIM_OC_PRE_LOAD_DISABLE
return none
void TIM_ConfigOc4Preload(TIM_Module *TIMx, uint32_t TIM_OCPreload)Enables or disables the TIMx peripheral Preload register on CCDAT4.
name TIM_ConfigOc4Preload
fun Enables or disables the TIMx peripheral Preload register on CCDAT4.
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
- GTIM1
- GTIM2
- GTIM3
- GTIM4
- GTIM5
param TIM_OCPreload
- TIM_OC_PRE_LOAD_ENABLE
- TIM_OC_PRE_LOAD_DISABLE
return none
void TIM_ConfigOc5Preload(TIM_Module *TIMx, uint32_t TIM_OCPreload)Enables or disables the TIMx peripheral Preload register on CCDAT5.
name TIM_ConfigOc5Preload
fun Enables or disables the TIMx peripheral Preload register on CCDAT5.
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
param TIM_OCPreload
- TIM_OC_PRE_LOAD_ENABLE
- TIM_OC_PRE_LOAD_DISABLE
return none
void TIM_ConfigOc6Preload(TIM_Module *TIMx, uint32_t TIM_OCPreload)Enables or disables the TIMx peripheral Preload register on CCDAT6.
name TIM_ConfigOc6Preload
fun Enables or disables the TIMx peripheral Preload register on CCDAT6.
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
param TIM_OCPreload
- TIM_OC_PRE_LOAD_ENABLE
- TIM_OC_PRE_LOAD_DISABLE
return none
void TIM_ConfigOc7Preload(TIM_Module *TIMx, uint32_t TIM_OCPreload)Enables or disables the TIMx peripheral Preload register on CCDAT7.
name TIM_ConfigOc7Preload
fun Enables or disables the TIMx peripheral Preload register on CCDAT7.
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
param TIM_OCPreload
- TIM_OC_PRE_LOAD_ENABLE
- TIM_OC_PRE_LOAD_DISABLE
return none
void TIM_ConfigOc8Preload(TIM_Module *TIMx, uint32_t TIM_OCPreload)Enables or disables the TIMx peripheral Preload register on CCDAT8.
name TIM_ConfigOc8Preload
fun Enables or disables the TIMx peripheral Preload register on CCDAT8.
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
param TIM_OCPreload
- TIM_OC_PRE_LOAD_ENABLE
- TIM_OC_PRE_LOAD_DISABLE
return none
void TIM_ConfigOc9Preload(TIM_Module *TIMx, uint32_t TIM_OCPreload)Enables or disables the TIMx peripheral Preload register on CCDAT9.
name TIM_ConfigOc9Preload
fun Enables or disables the TIMx peripheral Preload register on CCDAT9.
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
param TIM_OCPreload
- TIM_OC_PRE_LOAD_ENABLE
- TIM_OC_PRE_LOAD_DISABLE
return none
void TIM_ConfigOc1Fast(TIM_Module *TIMx, uint32_t TIM_OCFast)Configures the TIMx Output Compare 1 Fast feature.
name TIM_ConfigOc1Fast
fun Configures the TIMx Output Compare 1 Fast feature.
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
- GTIM1
- GTIM2
- GTIM3
- GTIM4
param TIM_OCFast
- TIM_OC_FAST_ENABLE
- TIM_OC_FAST_DISABLE
return none
void TIM_ConfigOc2Fast(TIM_Module *TIMx, uint32_t TIM_OCFast)Configures the TIMx Output Compare 2 Fast feature.
name TIM_ConfigOc2Fast
fun Configures the TIMx Output Compare 2 Fast feature.
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
- GTIM1
- GTIM2
- GTIM3
- GTIM4
param TIM_OCFast
- TIM_OC_FAST_ENABLE
- TIM_OC_FAST_DISABLE
return none
void TIM_ConfigOc3Fast(TIM_Module *TIMx, uint32_t TIM_OCFast)Configures the TIMx Output Compare 3 Fast feature.
name TIM_ConfigOc3Fast
fun Configures the TIMx Output Compare 3 Fast feature.
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
- GTIM1
- GTIM2
- GTIM3
- GTIM4
param TIM_OCFast
- TIM_OC_FAST_ENABLE
- TIM_OC_FAST_DISABLE
return none
void TIM_ConfigOc4Fast(TIM_Module *TIMx, uint32_t TIM_OCFast)Configures the TIMx Output Compare 4 Fast feature.
name TIM_ConfigOc4Fast
fun Configures the TIMx Output Compare 4 Fast feature.
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
- GTIM1
- GTIM2
- GTIM3
- GTIM4
param TIM_OCFast
- TIM_OC_FAST_ENABLE
- TIM_OC_FAST_DISABLE
return none
void TIM_ConfigOc5Fast(TIM_Module *TIMx, uint32_t TIM_OCFast)Configures the TIMx Output Compare 5 Fast feature.
name TIM_ConfigOc5Fast
fun Configures the TIMx Output Compare 5 Fast feature.
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
param TIM_OCFast
- TIM_OC_FAST_ENABLE
- TIM_OC_FAST_DISABLE
return none
void TIM_ConfigOc6Fast(TIM_Module *TIMx, uint32_t TIM_OCFast)Configures the TIMx Output Compare 6 Fast feature.
name TIM_ConfigOc6Fast
fun Configures the TIMx Output Compare 6 Fast feature.
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
param TIM_OCFast
- TIM_OC_FAST_ENABLE
- TIM_OC_FAST_DISABLE
return none
void TIM_ClrOc1Ref(TIM_Module *TIMx, uint32_t TIM_OCClear)Clears or safeguards the OCREF1 signal on an external event
name TIM_ClrOc1Ref
fun Clears or safeguards the OCREF1 signal on an external event
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
- GTIM1
- GTIM2
- GTIM3
- GTIM4
param TIM_OCPreload
- TIM_OC_CLR_ENABLE
- TIM_OC_CLR_DISABLE
return none
void TIM_ClrOc2Ref(TIM_Module *TIMx, uint32_t TIM_OCClear)Clears or safeguards the OCREF2 signal on an external event
name TIM_ClrOc2Ref
fun Clears or safeguards the OCREF2 signal on an external event
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
- GTIM1
- GTIM2
- GTIM3
- GTIM4
param TIM_OCPreload
- TIM_OC_CLR_ENABLE
- TIM_OC_CLR_DISABLE
return none
void TIM_ClrOc3Ref(TIM_Module *TIMx, uint32_t TIM_OCClear)Clears or safeguards the OCREF3 signal on an external event
name TIM_ClrOc3Ref
fun Clears or safeguards the OCREF3 signal on an external event
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
- GTIM1
- GTIM2
- GTIM3
- GTIM4
param TIM_OCPreload
- TIM_OC_CLR_ENABLE
- TIM_OC_CLR_DISABLE
return none
void TIM_ClrOc4Ref(TIM_Module *TIMx, uint32_t TIM_OCClear)Clears or safeguards the OCREF4 signal on an external event
name TIM_ClrOc4Ref
fun Clears or safeguards the OCREF4 signal on an external event
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
- GTIM1
- GTIM2
- GTIM3
param TIM_OCPreload
- TIM_OC_CLR_ENABLE
- TIM_OC_CLR_DISABLE
return none
void TIM_ClrOc5Ref(TIM_Module *TIMx, uint32_t TIM_OCClear)Clears or safeguards the OCREF5 signal on an external event
name TIM_ClrOc5Ref
fun Clears or safeguards the OCREF5 signal on an external event
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
param TIM_OCPreload
- TIM_OC_CLR_ENABLE
- TIM_OC_CLR_DISABLE
return none
void TIM_ClrOc6Ref(TIM_Module *TIMx, uint32_t TIM_OCClear)Clears or safeguards the OCREF6 signal on an external event
name TIM_ClrOc6Ref
fun Clears or safeguards the OCREF6 signal on an external event
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
param TIM_OCPreload
- TIM_OC_CLR_ENABLE
- TIM_OC_CLR_DISABLE
return none
void TIM_ClrOcRefInputSource(TIM_Module *TIMx, uint32_t OCRefClearInputSelect, uint32_t OCRefClearInputSource)Set the OCREF clear input source
name TIM_ClrOcRefInputSource
fun Set the OCREF clear input source
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
- GTIM1
- GTIM2
- GTIM3
- GTIM4
param OCRefClearInputSelect
- TIM_ETRSEL
- TIM_CLRSEL
param OCRefClearInputSource
- TIM_CAPETRSEL_0
- TIM_CAPETRSEL_1
- TIM_CAPETRSEL_2
- TIM_CAPETRSEL_3
- TIM_CAPETRSEL_4
- TIM_CAPETRSEL_5
- TIM_OCCLRSEL_0
- TIM_OCCLRSEL_1
- TIM_OCCLRSEL_2
return none
void TIM_ConfigOc1Polarity(TIM_Module *TIMx, uint32_t OcPolarity)Configures the TIMx channel 1 polarity.
name TIM_ConfigOc1Polarity
fun Configures the TIMx channel 1 polarity.
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
- GTIM1
- GTIM2
- GTIM3
- GTIM4
param TIM_OCPreload
- TIM_OC_POLARITY_HIGH
- TIM_OC_POLARITY_LOW
return none
void TIM_ConfigOc1NPolarity(TIM_Module *TIMx, uint32_t OcNPolarity)Configures the TIMx channel 1N polarity.
name TIM_ConfigOc1NPolarity
fun Configures the TIMx channel 1N polarity.
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
- GTIM3
- GTIM4
param TIM_OCPreload
- TIM_OCN_POLARITY_HIGH
- TIM_OCN_POLARITY_LOW
return none
void TIM_ConfigOc2Polarity(TIM_Module *TIMx, uint32_t OcPolarity)Configures the TIMx channel 2 polarity.
name TIM_ConfigOc2Polarity
fun Configures the TIMx channel 2 polarity.
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
- GTIM1
- GTIM2
- GTIM3
- GTIM4
param TIM_OCPreload
- TIM_OC_POLARITY_HIGH
- TIM_OC_POLARITY_LOW
return none
void TIM_ConfigOc2NPolarity(TIM_Module *TIMx, uint32_t OcNPolarity)Configures the TIMx channel 2N polarity.
name TIM_ConfigOc2NPolarity
fun Configures the TIMx channel 2N polarity.
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
param TIM_OCPreload
- TIM_OCN_POLARITY_HIGH
- TIM_OCN_POLARITY_LOW
return none
void TIM_ConfigOc3Polarity(TIM_Module *TIMx, uint32_t OcPolarity)Configures the TIMx channel 3 polarity.
name TIM_ConfigOc3Polarity
fun Configures the TIMx channel 3 polarity.
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
- GTIM1
- GTIM2
- GTIM3
- GTIM4
param TIM_OCPreload
- TIM_OC_POLARITY_HIGH
- TIM_OC_POLARITY_LOW
return none
void TIM_ConfigOc3NPolarity(TIM_Module *TIMx, uint32_t OcNPolarity)Configures the TIMx channel 3N polarity.
name TIM_ConfigOc3NPolarity
fun Configures the TIMx channel 3N polarity.
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
param TIM_OCPreload
- TIM_OCN_POLARITY_HIGH
- TIM_OCN_POLARITY_LOW
return none
void TIM_ConfigOc4Polarity(TIM_Module *TIMx, uint32_t OcPolarity)Configures the TIMx channel 4 polarity.
name TIM_ConfigOc4Polarity
fun Configures the TIMx channel 4 polarity.
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
- GTIM1
- GTIM2
- GTIM3
- GTIM4
param TIM_OCPreload
- TIM_OC_POLARITY_HIGH
- TIM_OC_POLARITY_LOW
return none
void TIM_ConfigOc4NPolarity(TIM_Module *TIMx, uint32_t OcNPolarity)Configures the TIMx channel 4N polarity.
name TIM_ConfigOc4NPolarity
fun Configures the TIMx channel 4N polarity.
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
param TIM_OCPreload
- TIM_OCN_POLARITY_HIGH
- TIM_OCN_POLARITY_LOW
return none
void TIM_ConfigOc5Polarity(TIM_Module *TIMx, uint32_t OcPolarity)Configures the TIMx channel 5 polarity.
name TIM_ConfigOc5Polarity
fun Configures the TIMx channel 5 polarity.
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
param TIM_OCPreload
- TIM_OC_POLARITY_HIGH
- TIM_OC_POLARITY_LOW
return none
void TIM_ConfigOc6Polarity(TIM_Module *TIMx, uint32_t OcPolarity)Configures the TIMx channel 6 polarity.
name TIM_ConfigOc6Polarity
fun Configures the TIMx channel 6 polarity.
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
param TIM_OCPreload
- TIM_OC_POLARITY_HIGH
- TIM_OC_POLARITY_LOW
return none
void TIM_EnableCapCmpCh(TIM_Module *TIMx, uint32_t Channel, uint32_t TIM_CCx)Enables or disables the TIM Capture Compare Channel x.
name TIM_EnableCapCmpCh
fun Enables or disables the TIM Capture Compare Channel x.
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
- GTIM1
- GTIM2
- GTIM3
- GTIM4
param Channel
- TIM_CH_1
- TIM_CH_2
- TIM_CH_3
- TIM_CH_4
- TIM_CH_5
- TIM_CH_6
param TIM_CCx
- TIM_CAP_CMP_ENABLE
- TIM_CAP_CMP_DISABLE
return none
void TIM_EnableCapCmpChN(TIM_Module *TIMx, uint32_t Channel, uint32_t TIM_CCxN)Enables or disables the TIM Capture Compare Channel xN.
name TIM_EnableCapCmpChN
fun Enables or disables the TIM Capture Compare Channel xN.
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
- GTIM3
- GTIM4
param Channel
- TIM_CH_1
- TIM_CH_2
- TIM_CH_3
- TIM_CH_4
param TIM_CCx
- TIM_CAP_CMP_N_ENABLE
- TIM_CAP_CMP_N_DISABLE
return none
void TIM_SetCmp1(TIM_Module *TIMx, uint32_t Compare1)Sets the TIMx Capture Compare1 Register value
name TIM_SetCmp1
fun Sets the TIMx Capture Compare1 Register value
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
- GTIM1
- GTIM2
- GTIM3
- GTIM4
param Compare1
- Compare1 can be a number between 0x00000000 and 0xFFFFFFFF
return none
void TIM_SetCmp2(TIM_Module *TIMx, uint32_t Compare2)Sets the TIMx Capture Compare2 Register value
name TIM_SetCmp2
fun Sets the TIMx Capture Compare2 Register value
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
- GTIM1
- GTIM2
- GTIM3
- GTIM4
param Compare2
- Compare2 can be a number between 0x00000000 and 0xFFFFFFFF
return none
void TIM_SetCmp3(TIM_Module *TIMx, uint32_t Compare3)Sets the TIMx Capture Compare3 Register value
name TIM_SetCmp3
fun Sets the TIMx Capture Compare3 Register value
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
- GTIM1
- GTIM2
- GTIM3
- GTIM4
param Compare3
- Compare3 can be a number between 0x00000000 and 0xFFFFFFFF
return none
void TIM_SetCmp4(TIM_Module *TIMx, uint32_t Compare4)Sets the TIMx Capture Compare4 Register value
name TIM_SetCmp4
fun Sets the TIMx Capture Compare4 Register value
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
- GTIM1
- GTIM2
- GTIM3
- GTIM4
param Compare4
- Compare4 can be a number between 0x00000000 and 0xFFFFFFFF
return none
void TIM_SetCmp5(TIM_Module *TIMx, uint16_t Compare5)Sets the TIMx Capture Compare5 Register value
name TIM_SetCmp5
fun Sets the TIMx Capture Compare5 Register value
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
param Compare5
- Compare5 can be a number between 0x0000 and 0xFFFF
return none
void TIM_SetCmp6(TIM_Module *TIMx, uint16_t Compare6)Sets the TIMx Capture Compare6 Register value
name TIM_SetCmp6
fun Sets the TIMx Capture Compare6 Register value
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
param Compare6
- Compare6 can be a number between 0x0000 and 0xFFFF
return none
void TIM_SetCmp7(TIM_Module *TIMx, uint16_t Compare7)Sets the TIMx Capture Compare7 Register value
name TIM_SetCmp7
fun Sets the TIMx Capture Compare7 Register value
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
param Compare7
- Compare7 can be a number between 0x0000 and 0xFFFF
return none
void TIM_SetCmp8(TIM_Module *TIMx, uint16_t Compare8)Sets the TIMx Capture Compare8 Register value
name TIM_SetCmp8
fun Sets the TIMx Capture Compare8 Register value
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
param Compare8
- Compare8 can be a number between 0x0000 and 0xFFFF
return none
void TIM_SetCmp9(TIM_Module *TIMx, uint16_t Compare9)Sets the TIMx Capture Compare9 Register value
name TIM_SetCmp9
fun Sets the TIMx Capture Compare9 Register value
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
param Compare9
- Compare9 can be a number between 0x0000 and 0xFFFF
return none
void TIM_SetCmp1D(TIM_Module *TIMx, uint16_t compare1D)Sets the CCDDAT1[31:16] in TIMx_CCDAT1 register
name TIM_SetCmp1D
fun Sets the CCDDAT1[31:16] in TIMx_CCDAT1 register
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
param compare1D
- compare1D can be a number between 0x0000 and 0xFFFF
return none
void TIM_SetCmp2D(TIM_Module *TIMx, uint16_t compare2D)Sets the CCDDAT2[31:16] in TIMx_CCDAT2 register
name TIM_SetCmp2D
fun Sets the CCDDAT2[31:16] in TIMx_CCDAT2 register
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
param compare2D
- compare2D can be a number between 0x0000 and 0xFFFF
return none
void TIM_SetCmp3D(TIM_Module *TIMx, uint16_t compare3D)Sets the CCDDAT3[31:16] in TIMx_CCDAT3 register
name TIM_SetCmp3D
fun Sets the CCDDAT3[31:16] in TIMx_CCDAT3 register
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
param compare3D
- compare3D can be a number between 0x0000 and 0xFFFF
return none
void TIM_SetCmp4D(TIM_Module *TIMx, uint16_t compare4D)Sets the CCDDAT4[31:16] in TIMx_CCDAT4 register
name TIM_SetCmp4D
fun Sets the CCDDAT4[31:16] in TIMx_CCDAT4 register
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
param compare4D
- compare4D can be a number between 0x0000 and 0xFFFF
return none
void TIM_AsymmetricEnable(TIM_Module *TIMx, FunctionalState Cmd)Enable or disable asymmetric mode in center-aligned.
name TIM_AsymmetricEnable.
fun Enable or disable asymmetric mode in center-aligned.
param TIMx:
- ATIM1
- ATIM2
- GTIM3
- GTIM4
param Cmd
- ENABLE
- DISABLE
return none
void TIM_SelectCenterAlignTrig(TIM_Module *TIMx, uint32_t TIM_CenterAlignTriggerSource)Setting the trigger mode in central alignment mode.
name TIM_SelectCenterAlignTrig.
fun Setting the trigger mode in central alignment mode.
param TIMx:
- ATIM1
- ATIM2
param TIM_CenterAlignTriggerSource
- TIM_UP_COUNTING
- TIM_DOWN_COUNTING
- TIM_UP_DOWN_COUNTING
return none
void TIM_OCxRefTriggerADC(TIM_Module *TIMx, uint32_t OCxRef, FunctionalState Cmd)Enable or disable OCxREF to trigger ADC(x = 4,7,8 or 9).
name TIM_OCxRefTriggerADC.
fun Enable or disable OCxREF to trigger ADC(x = 4,7,8 or 9).
param TIMx:
- ATIM1
- ATIM2
param OCxRef
- TIM_CTRL2_TRIG4
- TIM_CTRL2_TRIG7
- TIM_CTRL2_TRIG8
- TIM_CTRL2_TRIG9
param Cmd
- ENABLE
- DISABLE
return none
void TIM_ICInit(TIM_Module *TIMx, const TIM_ICInitType *TIM_ICInitStruct)Initializes the TIM peripheral according to the specified parameters in the TIM_ICInitStruct.
name TIM_ICInit
fun Initializes the TIM peripheral according to the specified
parameters in the TIM_ICInitStruct.
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
- GTIM1
- GTIM2
- GTIM3
- GTIM4
param TIM_ICInitStruct: refer to the definition of TIM_ICInitType
- Channel
* TIM_CH_1
* TIM_CH_2
* TIM_CH_3
* TIM_CH_4
- ICPolarity
* TIM_IC_POLARITY_RISING
* TIM_IC_POLARITY_FALLING
- ICSelection
* TIM_IC_SELECTION_DIRECTTI
* TIM_IC_SELECTION_INDIRECTTI
* TIM_IC_SELECTION_TRC
- ICPrescaler
* TIM_IC_PSC_DIV1
* TIM_IC_PSC_DIV2
* TIM_IC_PSC_DIV4
* TIM_IC_PSC_DIV8
- ICFilter
* ICFilter can be a number between 0x0 and 0xF
return none
void TIM_ConfigPwmIc(TIM_Module *TIMx, const TIM_ICInitType *TIM_ICInitStruct)Configures the TIM peripheral according to the specified parameters in the TIM_ICInitStruct to measure an external PWM signal.
name TIM_ConfigPwmIc
fun Configures the TIM peripheral according to the specified
parameters in the TIM_ICInitStruct to measure an external PWM signal.
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
- GTIM1
- GTIM2
- GTIM3
- GTIM4
param TIM_ICInitStruct: refer to the definition of TIM_ICInitType
- Channel
* TIM_CH_1
* TIM_CH_2
- ICPolarity
* TIM_IC_POLARITY_RISING
* TIM_IC_POLARITY_FALLING
- ICSelection
* TIM_IC_SELECTION_DIRECTTI
* TIM_IC_SELECTION_INDIRECTTI
- ICPrescaler
* TIM_IC_PSC_DIV1
* TIM_IC_PSC_DIV2
* TIM_IC_PSC_DIV4
* TIM_IC_PSC_DIV8
- ICFilter
* ICFilter can be a number between 0x0 and 0xF
return none
void ConfigTI1(TIM_Module *TIMx, uint32_t ICPolarity, uint32_t ICSelection, uint32_t ICFilter)Configure the TI1 as Input.
name ConfigTI1
fun Configure the TI1 as Input.
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
- GTIM1
- GTIM2
- GTIM3
- GTIM4
param ICPolarity
- TIM_IC_POLARITY_RISING
- TIM_IC_POLARITY_FALLING
param ICSelection
- TIM_IC_SELECTION_DIRECTTI
- TIM_IC_SELECTION_INDIRECTTI
- TIM_IC_SELECTION_TRC
param ICFilter
- ICFilter can be a number between 0x0 and 0xF
return none
void ConfigTI2(TIM_Module *TIMx, uint32_t ICPolarity, uint32_t ICSelection, uint32_t ICFilter)Configure the TI2 as Input.
name ConfigTI2
fun Configure the TI2 as Input.
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
- GTIM1
- GTIM2
- GTIM3
- GTIM4
param ICPolarity
- TIM_IC_POLARITY_RISING
- TIM_IC_POLARITY_FALLING
param ICSelection
- TIM_IC_SELECTION_DIRECTTI
- TIM_IC_SELECTION_INDIRECTTI
- TIM_IC_SELECTION_TRC
param ICFilter
- ICFilter can be a number between 0x0 and 0xF
return none
void ConfigTI3(TIM_Module *TIMx, uint32_t ICPolarity, uint32_t ICSelection, uint32_t ICFilter)Configure the TI3 as Input.
name ConfigTI3
fun Configure the TI3 as Input.
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
- GTIM1
- GTIM2
- GTIM3
- GTIM4
param ICPolarity
- TIM_IC_POLARITY_RISING
- TIM_IC_POLARITY_FALLING
param ICSelection
- TIM_IC_SELECTION_DIRECTTI
- TIM_IC_SELECTION_INDIRECTTI
- TIM_IC_SELECTION_TRC
param ICFilter
- ICFilter can be a number between 0x0 and 0xF
return none
void ConfigTI4(TIM_Module *TIMx, uint32_t ICPolarity, uint32_t ICSelection, uint32_t ICFilter)Configure the TI4 as Input.
name ConfigTI4
fun Configure the TI4 as Input.
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
- GTIM1
- GTIM2
- GTIM3
- GTIM4
param ICPolarity
- TIM_IC_POLARITY_RISING
- TIM_IC_POLARITY_FALLING
param ICSelection
- TIM_IC_SELECTION_DIRECTTI
- TIM_IC_SELECTION_INDIRECTTI
- TIM_IC_SELECTION_TRC
param ICFilter
- ICFilter can be a number between 0x0 and 0xF
return none
void TIM_SetInCap1Prescaler(TIM_Module *TIMx, uint32_t ICPrescaler)Sets the TIMx Input Capture 1 prescaler.
name TIM_SetInCap1Prescaler
fun Sets the TIMx Input Capture 1 prescaler.
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
- GTIM1
- GTIM2
- GTIM3
- GTIM4
param ICPrescaler
- TIM_IC_PSC_DIV1
- TIM_IC_PSC_DIV2
- TIM_IC_PSC_DIV4
- TIM_IC_PSC_DIV8
return none
void TIM_SetInCap2Prescaler(TIM_Module *TIMx, uint32_t ICPrescaler)Sets the TIMx Input Capture 2 prescaler.
name TIM_SetInCap2Prescaler
fun Sets the TIMx Input Capture 2 prescaler.
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
- GTIM1
- GTIM2
- GTIM3
- GTIM4
param ICPrescaler
- TIM_IC_PSC_DIV1
- TIM_IC_PSC_DIV2
- TIM_IC_PSC_DIV4
- TIM_IC_PSC_DIV8
return none
void TIM_SetInCap3Prescaler(TIM_Module *TIMx, uint32_t ICPrescaler)Sets the TIMx Input Capture 3 prescaler.
name TIM_SetInCap3Prescaler
fun Sets the TIMx Input Capture 3 prescaler.
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
- GTIM1
- GTIM2
- GTIM3
- GTIM4
param ICPrescaler
- TIM_IC_PSC_DIV1
- TIM_IC_PSC_DIV2
- TIM_IC_PSC_DIV4
- TIM_IC_PSC_DIV8
return none
void TIM_SetInCap4Prescaler(TIM_Module *TIMx, uint32_t ICPrescaler)Sets the TIMx Input Capture 4 prescaler.
name TIM_SetInCap4Prescaler
fun Sets the TIMx Input Capture 4 prescaler.
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
- GTIM1
- GTIM2
- GTIM3
- GTIM4
param ICPrescaler
- TIM_IC_PSC_DIV1
- TIM_IC_PSC_DIV2
- TIM_IC_PSC_DIV4
- TIM_IC_PSC_DIV8
return none
uint32_t TIM_GetCap1(const TIM_Module *TIMx)Gets the TIMx Input Capture 1 value.
name TIM_GetCap1
fun Gets the TIMx Input Capture 1 value.
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
- GTIM1
- GTIM2
- GTIM3
- GTIM4
return Capture Compare 1 Register value.
uint32_t TIM_GetCap2(const TIM_Module *TIMx)Gets the TIMx Input Capture 2 value.
name TIM_GetCap2
fun Gets the TIMx Input Capture 2 value.
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
- GTIM1
- GTIM2
- GTIM3
- GTIM4
return Capture Compare 2 Register value.
uint32_t TIM_GetCap3(const TIM_Module *TIMx)Gets the TIMx Input Capture 3 value.
name TIM_GetCap3
fun Gets the TIMx Input Capture 3 value.
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
- GTIM1
- GTIM2
- GTIM3
- GTIM4
return Capture Compare 3 Register value.
uint32_t TIM_GetCap4(const TIM_Module *TIMx)Gets the TIMx Input Capture 4 value.
name TIM_GetCap4
fun Gets the TIMx Input Capture 4 value.
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
- GTIM1
- GTIM2
- GTIM3
- GTIM4
return Capture Compare 4 Register value.
uint16_t TIM_GetCap5(const TIM_Module *TIMx)Gets the TIMx Input Capture 5 value.
name TIM_GetCap5
fun Gets the TIMx Input Capture 5 value.
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
return Capture Compare 5 Register value.
uint16_t TIM_GetCap6(const TIM_Module *TIMx)Gets the TIMx Input Capture 6 value.
name TIM_GetCap6
fun Gets the TIMx Input Capture 6 value.
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
return Capture Compare 6 Register value.
uint16_t TIM_GetCap7(const TIM_Module *TIMx)Gets the TIMx Input Capture 7 value.
name TIM_GetCap7
fun Gets the TIMx Input Capture 7 value.
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
return Capture Compare 7 Register value.
uint16_t TIM_GetCap8(const TIM_Module *TIMx)Gets the TIMx Input Capture 8 value.
name TIM_GetCap8
fun Gets the TIMx Input Capture 8 value.
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
return Capture Compare 8 Register value.
uint16_t TIM_GetCap9(const TIM_Module *TIMx)Gets the TIMx Input Capture 9 value.
name TIM_GetCap9
fun Gets the TIMx Input Capture 9 value.
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
return Capture Compare 9 Register value.
uint16_t TIM_GetCap1D(const TIM_Module *TIMx)Gets the TIMx Input Capture 1D value.
name TIM_GetCap1D
fun Gets the TIMx Input Capture 1D value.
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
return Capture Compare 1D Register value.
uint16_t TIM_GetCap2D(const TIM_Module *TIMx)Gets the TIMx Input Capture 2D value.
name TIM_GetCap2D
fun Gets the TIMx Input Capture 2D value.
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
return Capture Compare 2D Register value.
uint16_t TIM_GetCap3D(const TIM_Module *TIMx)Gets the TIMx Input Capture 3D value.
name TIM_GetCap3D
fun Gets the TIMx Input Capture 3D value.
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
return Capture Compare 3D Register value.
uint16_t TIM_GetCap4D(const TIM_Module *TIMx)Gets the TIMx Input Capture 4D value.
name TIM_GetCap4D
fun Gets the TIMx Input Capture 4D value.
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
return Capture Compare 4D Register value.
void TIM_IC1FiltConfig(TIM_Module *TIMx, const TIM_FiltInitType *TIM_FiltInitStruct)Config the filter of channel1.
name TIM_IC1FiltConfig
fun Config the filter of channel1.
param TIMx:
- GTIM1
- GTIM2
- GTIM3
- GTIM4
param TIM_FiltInitStruct:
- refer to the definition of TIM_FiltInitType
return none
void TIM_IC2FiltConfig(TIM_Module *TIMx, const TIM_FiltInitType *TIM_FiltInitStruct)Config the filter of channel2.
name TIM_IC2FiltConfig
fun Config the filter of channel2.
param TIMx:
- GTIM1
- GTIM2
- GTIM3
- GTIM4
param TIM_FiltInitStruct:
- refer to the definition of TIM_FiltInitType
return none
void TIM_IC3FiltConfig(TIM_Module *TIMx, const TIM_FiltInitType *TIM_FiltInitStruct)Config the filter of channel3.
name TIM_IC3FiltConfig
fun Config the filter of channel3.
param TIMx:
- GTIM1
- GTIM2
- GTIM3
- GTIM4
param TIM_FiltInitStruct:
- refer to the definition of TIM_FiltInitType
return none
void TIM_IC4FiltConfig(TIM_Module *TIMx, const TIM_FiltInitType *TIM_FiltInitStruct)Config the filter of channel4.
name TIM_IC4FiltConfig
fun Config the filter of channel4.
param TIMx:
- GTIM1
- GTIM2
- GTIM3
- GTIM4
param TIM_FiltInitStruct:
- refer to the definition of TIM_FiltInitType
return none
void TIM_IC1FiltEnable(TIM_Module *TIMx, FunctionalState Cmd)Enable or disable the filter of channel1.
name TIM_IC1FiltEnable
fun Enable or disable the filter of channel1.
param TIMx:
- GTIM1
- GTIM2
- GTIM3
- GTIM4
param Cmd :
- ENABLE
- DISABLE
return none
void TIM_IC2FiltEnable(TIM_Module *TIMx, FunctionalState Cmd)Enable or disable the filter of channel2.
name TIM_IC2FiltEnable
fun Enable or disable the filter of channel2.
param TIMx:
- GTIM1
- GTIM2
- GTIM3
- GTIM4
param Cmd :
- ENABLE
- DISABLE
return none
void TIM_IC3FiltEnable(TIM_Module *TIMx, FunctionalState Cmd)Enable or disable the filter of channel3.
name TIM_IC3FiltEnable
fun Enable or disable the filter of channel3.
param TIMx:
- GTIM1
- GTIM2
- GTIM3
- GTIM4
param Cmd :
- ENABLE
- DISABLE
return none
void TIM_IC4FiltEnable(TIM_Module *TIMx, FunctionalState Cmd)Enable or disable the filter of channel4.
name TIM_IC4FiltEnable
fun Enable or disable the filter of channel4.
param TIMx:
- GTIM1
- GTIM2
- GTIM3
- GTIM4
param Cmd :
- ENABLE
- DISABLE
return none
FlagStatus TIM_GetFiltStatus(const TIM_Module *TIMx, uint32_t TIM_FiltFlag)Checks the specified filter status.
name TIM_GetFiltStatus
fun Checks the specified filter status.
param TIMx (The input parameters must be the following values):
- GTIM1
- GTIM2
- GTIM3
- GTIM4
param TIM_FiltFlag :
- TIM_C1FILTO
- TIM_C2FILTO
- TIM_C3FILTO
- TIM_C4FILTO
return The new state of TIM_FiltFlag (SET or RESET).
void TIM_EnableCtrlPwmOutputs(TIM_Module *TIMx, FunctionalState Cmd)Enables or disables the TIM peripheral Main Outputs.
name TIM_EnableCtrlPwmOutputs
fun Enables or disables the TIM peripheral Main Outputs.
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
- GTIM3
- GTIM4
param Cmd :
- ENABLE
- DISABLE
return none
void TIM_ConfigBkdt(TIM_Module *TIMx, const TIM_BDTRInitType *TIM_BDTRInitStruct)Configures the: Break feature, dead time, Lock level, the OSSI, the OSSR State and the AOE(automatic output enable).
name TIM_ConfigBkdt
fun Configures the: Break feature, dead time, Lock level, the OSSI,
the OSSR State and the AOE(automatic output enable).
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
- GTIM3
- GTIM4
param TIM_BDTRInitStruct: refer to the definition of TIM_BDTRInitType
- OSSRState
* TIM_OSSR_STATE_ENABLE
* TIM_OSSR_STATE_DISABLE
- OSSIState
* TIM_OSSI_STATE_ENABLE
* TIM_OSSI_STATE_DISABLE
- LOCKLevel
* TIM_LOCK_LEVEL_OFF
* TIM_LOCK_LEVEL_1
* TIM_LOCK_LEVEL_2
* TIM_LOCK_LEVEL_3
- DeadTime
* DeadTime can be a number between 0x00 and 0xFF
- Break
* TIM_BREAK_IN_ENABLE
* TIM_BREAK_IN_DISABLE
- BreakPolarity
* TIM_BREAK_POLARITY_LOW
* TIM_BREAK_POLARITY_HIGH
- Bidirection
* TIM_BREAK_BID_ENABLE
* TIM_BREAK_BID_DISABLE
- AutomaticOutput
* TIM_AUTO_OUTPUT_ENABLE
* TIM_AUTO_OUTPUT_DISABLE
return none
void TIM_BreakFiltConfig(TIM_Module *TIMx, const TIM_FiltInitType *TIM_FiltInitStruct)Config the filter of break input.
name TIM_BreakFiltConfig
fun Config the filter of break input.
param TIMx:
- ATIM1
- ATIM2
- GTIM3
- GTIM4
param TIM_FiltInitStruct:
- refer to the definition of TIM_FiltInitType
return none
void TIM_BreakFiltEnable(TIM_Module *TIMx, FunctionalState Cmd)Enable or disable the filter of break input.
name TIM_BreakFiltEnable
fun Enable or disable the filter of break input.
param TIMx:
- ATIM1
- ATIM2
- GTIM3
- GTIM4
param Cmd :
- ENABLE
- DISABLE
return none
void TIM_BreakInputSourceEnable(TIM_Module *TIMx, uint32_t Source, uint32_t Polarity, FunctionalState Cmd)Enable or disable the break input source , and set the polarity of the break input source.
name TIM_BreakInputSourceEnable
fun Enable or disable the break input source , and set the polarity of the break input source.
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
- GTIM3
- GTIM4
param Source
- TIM_BREAK_LOCKUP
- TIM_BREAK_PVD
- TIM_BREAK_IOM1
- TIM_BREAK_IOM2
- TIM_BREAK_IOM3
- TIM_BREAK_IOM4
- TIM_BREAK_IOM5
- TIM_BREAK_IOM6
- TIM_BREAK_IOM7
- TIM_BREAK_COMP1
- TIM_BREAK_COMP2
- TIM_BREAK_COMP3
param Polarity
- TIM_BREAK_SOURCE_POLARITY_INVERT
- TIM_BREAK_SOURCE_POLARITY_NONINVERT
param Cmd
- ENABLE
- DISABLE
return none
void TIM_BidirectionDisarm(TIM_Module *TIMx)Disarm bidirection of break.
name TIM_BidirectionDisarm
fun Disarm bidirection of break.
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
- GTIM3
- GTIM4
return none
void TIM_BidirectionRearm(TIM_Module *TIMx)Rearm bidirection of break.
name TIM_BidirectionRearm
fun Rearm bidirection of break.
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
- GTIM3
- GTIM4
return none
void TIM_SelectComEvt(TIM_Module *TIMx, FunctionalState Cmd)Selects the TIM peripheral Commutation event.
name TIM_SelectComEvt
fun Selects the TIM peripheral Commutation event.
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
- GTIM3
- GTIM4
param Cmd
- ENABLE
- DISABLE
return none
void TIM_SelectCapCmpDmaSrc(TIM_Module *TIMx, FunctionalState Cmd)Selects the TIMx peripheral Capture Compare DMA source.
name TIM_SelectCapCmpDmaSrc
fun Selects the TIMx peripheral Capture Compare DMA source.
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
- GTIM1
- GTIM2
- GTIM3
- GTIM4
param Cmd
- ENABLE
- DISABLE
return none
Use note: The implementation sets or clears the CCDSEL bit of TIMx->CTRL2 according to Cmd, selecting capture/compare events as the DMA request source.
void TIM_EnableCapCmpPreloadControl(TIM_Module *TIMx, FunctionalState Cmd)Sets or Resets the TIM peripheral Capture Compare Preload Control bit.
name TIM_EnableCapCmpPreloadControl
fun Sets or Resets the TIM peripheral Capture Compare Preload Control bit.
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
- GTIM3
- GTIM4
param Cmd
- ENABLE
- DISABLE
return none
Use note: The implementation sets or clears the CCPCTL bit of TIMx->CTRL2 according to Cmd.
FlagStatus TIM_GetCCENStatus(const TIM_Module *TIMx, uint32_t TIM_CCEN)Checks whether the specified TIM flag is set or not.
name TIM_GetCCENStatus
fun Checks whether the specified TIM flag is set or not.
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
- GTIM1
- GTIM2
- GTIM3
- GTIM4
param TIM_CCEN :
- TIM_CC1EN
- TIM_CC1NEN
- TIM_CC2EN
- TIM_CC2NEN
- TIM_CC3EN
- TIM_CC3NEN
- TIM_CC4EN
- TIM_CC4NEN
- TIM_CC5EN
- TIM_CC6EN
return The new state of TIM_FLAG (SET or RESET).
Use note: The implementation reads the capture/compare enable register TIMx->CCEN and ANDs it with TIM_CCEN, so it checks channel enable bits rather than an interrupt flag in STS.
void TIM_ConfigEncoderInterface(TIM_Module *TIMx, uint32_t TIM_EncoderMode, uint32_t TIM_IC1Polarity, uint32_t TIM_IC2Polarity)Configures the TIMx Encoder Interface.
name TIM_ConfigEncoderInterface
fun Configures the TIMx Encoder Interface.
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
- GTIM3
- GTIM4
param TIM_EncoderMode
- TIM_ENCODE_QUA_MODE_TI1
- TIM_ENCODE_QUA_MODE_TI2
- TIM_ENCODE_QUA_MODE_TI12
param TIM_IC1Polarity
- TIM_IC_POLARITY_FALLING
- TIM_IC_POLARITY_RISING
param TIM_IC2Polarity
- TIM_IC_POLARITY_FALLING
- TIM_IC_POLARITY_RISING
return none
void TIM_ConfigEncoderInterface2(TIM_Module *TIMx, uint32_t TIM_EncoderMode, uint32_t TIM_IC1Polarity, uint32_t TIM_IC2Polarity)Configures the TIMx Encoder Interface.
name TIM_ConfigEncoderInterface2
fun Configures the TIMx Encoder Interface.
param TIMx (The input parameters must be the following values):
- GTIM1
- GTIM2
param TIM_EncoderMode
- TIM_ENCODE2_QUA_MODE_TI1
- TIM_ENCODE2_QUA_MODE_TI2
- TIM_ENCODE2_QUA_MODE_TI12
- TIM_ENCODE2_QUA_MODE_SINGLE_TI1
- TIM_ENCODE2_QUA_MODE_SINGLE_TI2
- TIM_ENCODE2_DUL_CLKPLUS_MODE1
- TIM_ENCODE2_DUL_CLKPLUS_MODE2
- TIM_ENCODE2_SINGLE_CLKPLUS_MODE1
- TIM_ENCODE2_SINGLE_CLKPLUS_MODE2
- TIM_ENCODE2_CCW_MODE1
- TIM_ENCODE2_CCW_MODE2
param TIM_IC1Polarity
- TIM_IC_POLARITY_FALLING
- TIM_IC_POLARITY_RISING
param TIM_IC2Polarity
- TIM_IC_POLARITY_FALLING
- TIM_IC_POLARITY_RISING
return none
void TIM_TrgiLoadLvrToCNTEnable(TIM_Module *TIMx, FunctionalState Cmd)The TRGI signal triggers the loading of the ENCLVR value into the CNT.
name TIM_TrgiLoadLvrToCNTEnable
fun The TRGI signal triggers the loading of the ENCLVR value into the CNT.
param TIMx (The input parameters must be the following values):
- GTIM2
param Cmd :
- ENABLE
- DISABLE
return none
uint32_t TIM_GetLVR(const TIM_Module *TIMx)Get the TIMx LVR value.
name TIM_GetLVR
fun Get the TIMx LVR value.
param TIMx (The input parameters must be the following values):
- GTIM1
- GTIM2
return ENCLVR Register value.
void TIM_CH3LoadLvrToCNTEnable(TIM_Module *TIMx, FunctionalState Cmd)The CH3 triggers the loading of the ENCLVR value into the CNT.
name TIM_CH3LoadLvrToCNTEnable
fun The CH3 triggers the loading of the ENCLVR value into the CNT.
param TIMx (The input parameters must be the following values):
- GTIM1
- GTIM2
param Cmd :
- ENABLE
- DISABLE
return none
void TIM_CH3LoadLvrToCNTPolarity(TIM_Module *TIMx, uint32_t Polarity)Config CH3 Polarity to trigger ENCLVR value loading into the CNT.
name TIM_CH3LoadLvrToCNTPolarity
fun Config CH3 Polarity to trigger ENCLVR value loading into the CNT.
param TIMx (The input parameters must be the following values):
- GTIM1
- GTIM2
param Polarity :
- TIM_CH3_POLARITY_HIGH
- TIM_CH3_POLARITY_LOW
- TIM_CH3_POLARITY_RISING
- TIM_CH3_POLARITY_FALLING
return none
uint32_t TIM_GetENCDAT(const TIM_Module *TIMx)Gets the TIMx ENCDAT value.
name TIM_GetENCDAT
fun Gets the TIMx ENCDAT value.
param TIMx (The input parameters must be the following values):
- GTIM1
- GTIM2
return ENCDAT Register value.
uint32_t TIM_GetENCDATSign(const TIM_Module *TIMx)Get the sign of TIMx ENCDAT value.
name TIM_GetENCDATSign
fun Get the sign of TIMx ENCDAT value.
param TIMx (The input parameters must be the following values):
- GTIM1
- GTIM2
return Sign of TIMx ENCDAT value.
void TIM_ConfigInternalClk(TIM_Module *TIMx)Configures the TIMx internal Clock
name TIM_ConfigInternalClk
fun Configures the TIMx internal Clock
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
- GTIM1
- GTIM2
- GTIM3
- GTIM4
return none
void TIM_SelectInputTrig(TIM_Module *TIMx, uint32_t TIM_InputTriggerSource)Selects the Input Trigger source
name TIM_SelectInputTrig
fun Selects the Input Trigger source
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
- ATIM3
- GTIM1
- GTIM2
- GTIM3
- GTIM4
- GTIM5
- GTIM6
- GTIM7
- GTIM8
- GTIM9
- GTIM10
param TIM_InputTriggerSource:
- TIM_TRIG_SEL_IN_TR0
- TIM_TRIG_SEL_IN_TR1
- TIM_TRIG_SEL_IN_TR2
- TIM_TRIG_SEL_IN_TR3
- TIM_TRIG_SEL_IN_TR4
- TIM_TRIG_SEL_IN_TR5
- TIM_TRIG_SEL_TI1F_ED
- TIM_TRIG_SEL_TI1FP1
- TIM_TRIG_SEL_TI2FP2
- TIM_TRIG_SEL_ETRF
return none
void TIM_ConfigInternalTrigToExt(TIM_Module *TIMx, uint32_t TIM_InputTriggerSource)Configures the TIMx Internal Trigger as External Clock
name TIM_ConfigInternalTrigToExt
fun Configures the TIMx Internal Trigger as External Clock
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
- GTIM1
- GTIM2
- GTIM3
- GTIM4
param TIM_InputTriggerSource:
- TIM_TRIG_SEL_IN_TR0
- TIM_TRIG_SEL_IN_TR1
- TIM_TRIG_SEL_IN_TR2
- TIM_TRIG_SEL_IN_TR3
- TIM_TRIG_SEL_IN_TR4
- TIM_TRIG_SEL_IN_TR5
return none
void TIM_ConfigExtTrigAsClk(TIM_Module *TIMx, uint32_t TIM_TIxExternalCLKSource, uint32_t IcPolarity, uint32_t ICFilter)Configures the TIMx Trigger as External Clock
name TIM_ConfigExtTrigAsClk
fun Configures the TIMx Trigger as External Clock
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
- GTIM1
- GTIM2
- GTIM3
- GTIM4
param TIM_TIxExternalCLKSource:
- TIM_TRIG_SEL_TI1F_ED
- TIM_TRIG_SEL_TI1FP1
- TIM_TRIG_SEL_TI2FP2
param ICPolarity
- TIM_IC_POLARITY_RISING
- TIM_IC_POLARITY_FALLING
param ICFilter
- ICFilter can be a number between 0x0 and 0xF
return none
void TIM_ConfigExtClkMode1(TIM_Module *TIMx, uint32_t TIM_ETRInputSource, uint32_t TIM_ExtTRGPrescaler, uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter)Configures the External clock Mode1
name TIM_ConfigExtClkMode1
fun Configures the External clock Mode1
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
- GTIM1
- GTIM2
- GTIM3
- GTIM4
param TIM_ETRInputSource:
- TIM_CAPETRSEL_0
- TIM_CAPETRSEL_1
- TIM_CAPETRSEL_2
- TIM_CAPETRSEL_3
- TIM_CAPETRSEL_4
- TIM_CAPETRSEL_5
param TIM_ExtTRGPrescaler:
- TIM_EXT_TRG_PSC_OFF
- TIM_EXT_TRG_PSC_DIV2
- TIM_EXT_TRG_PSC_DIV4
- TIM_EXT_TRG_PSC_DIV8
param TIM_ExtTRGPolarity
- TIM_EXT_TRIG_POLARITY_INVERTED
- TIM_EXT_TRIG_POLARITY_NONINVERTED
param ExtTRGFilter
- ExtTRGFilter can be a number between 0x0 and 0xF
return none
void TIM_ConfigExtClkMode2(TIM_Module *TIMx, uint32_t TIM_ETRInputSource, uint32_t TIM_ExtTRGPrescaler, uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter)Configures the External clock Mode2
name TIM_ConfigExtClkMode2
fun Configures the External clock Mode2
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
- GTIM1
- GTIM2
- GTIM3
- GTIM4
param TIM_ETRInputSource:
- TIM_CAPETRSEL_0
- TIM_CAPETRSEL_1
- TIM_CAPETRSEL_2
- TIM_CAPETRSEL_3
- TIM_CAPETRSEL_4
- TIM_CAPETRSEL_5
param TIM_ExtTRGPrescaler:
- TIM_EXT_TRG_PSC_OFF
- TIM_EXT_TRG_PSC_DIV2
- TIM_EXT_TRG_PSC_DIV4
- TIM_EXT_TRG_PSC_DIV8
param TIM_ExtTRGPolarity
- TIM_EXT_TRIG_POLARITY_INVERTED
- TIM_EXT_TRIG_POLARITY_NONINVERTED
param ExtTRGFilter
- ExtTRGFilter can be a number between 0x0 and 0xF
return none
void TIM_ConfigExtTrig(TIM_Module *TIMx, uint32_t TIM_ExtTRGPrescaler, uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter)Configures the TIMx External Trigger (ETR).
name TIM_ConfigExtTrig
fun Configures the TIMx External Trigger (ETR).
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
- GTIM1
- GTIM2
- GTIM3
- GTIM4
param TIM_ExtTRGPrescaler:
- TIM_EXT_TRG_PSC_OFF
- TIM_EXT_TRG_PSC_DIV2
- TIM_EXT_TRG_PSC_DIV4
- TIM_EXT_TRG_PSC_DIV8
param TIM_ExtTRGPolarity
- TIM_EXT_TRIG_POLARITY_INVERTED
- TIM_EXT_TRIG_POLARITY_NONINVERTED
param ExtTRGFilter
- ExtTRGFilter can be a number between 0x0 and 0xF
return none
void TIM_SelectETRInputSource(TIM_Module *TIMx, uint32_t TIM_ETRInputSource)Configures the source of tim_etr_in.
name TIM_SelectETRInputSource
fun Configures the source of tim_etr_in.
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
- GTIM1
- GTIM2
- GTIM3
- GTIM4
param TIM_ETRInputSource:
- TIM_CAPETRSEL_0
- TIM_CAPETRSEL_1
- TIM_CAPETRSEL_2
- TIM_CAPETRSEL_3
- TIM_CAPETRSEL_4
- TIM_CAPETRSEL_5
return none
void TIM_SelectOutputTrig(TIM_Module *TIMx, uint32_t TIM_TRGOSource)Selects the TIMx Trigger Output Mode.
name TIM_SelectOutputTrig
fun Selects the TIMx Trigger Output Mode.
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
- GTIM1
- GTIM2
- GTIM3
- GTIM4
- BTIM1
- BTIM2
param TIM_TRGOSource
- TIM_TRGO_SRC_RESET
- TIM_TRGO_SRC_ENABLE
- TIM_TRGO_SRC_UPDATE
- TIM_TRGO_SRC_OC1
- TIM_TRGO_SRC_OC1REF
- TIM_TRGO_SRC_OC2REF
- TIM_TRGO_SRC_OC3REF
- TIM_TRGO_SRC_OC4REF
- TIM_TRGO_SRC_OC4_7_8_9REF
return none
void TIM_SelectOutputTrig2(TIM_Module *TIMx, uint32_t TIM_TRGO2Source)Selects the TIMx Trigger Output Mode.
name TIM_SelectOutputTrig2
fun Selects the TIMx Trigger Output Mode.
param TIMx (The input parameters must be the following values):
- ATIM1
param TIM_TRGO2Source
- TIM_TRGO2_SRC_RESET
- TIM_TRGO2_SRC_ENABLE
- TIM_TRGO2_SRC_UPDATE
- TIM_TRGO2_SRC_OC1
- TIM_TRGO2_SRC_OC1REF
- TIM_TRGO2_SRC_OC2REF
- TIM_TRGO2_SRC_OC3REF
- TIM_TRGO2_SRC_OC4REF
- TIM_TRGO2_SRC_OC5REF
- TIM_TRGO2_SRC_OC6REF
- LL_TIM_TRGO2_OC4_RISINGFALLING
- LL_TIM_TRGO2_OC6_RISINGFALLING
- LL_TIM_TRGO2_OC4_RISING_OC6_RISING
- LL_TIM_TRGO2_OC4_RISING_OC6_FALLING
- LL_TIM_TRGO2_OC5_RISING_OC6_RISING
- LL_TIM_TRGO2_OC5_RISING_OC6_FALLING
return none
void TIM_SelectSlaveMode(TIM_Module *TIMx, uint32_t TIM_SlaveMode)Selects the TIMx Slave Mode.
name TIM_SelectSlaveMode
fun Selects the TIMx Slave Mode.
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
- GTIM1
- GTIM2
- GTIM3
- GTIM4
param TIM_SlaveMode
- TIM_SLAVE_MODE_DISABLE
- TIM_SLAVE_MODE_RESET
- TIM_SLAVE_MODE_GATED
- TIM_SLAVE_MODE_TRIG
- TIM_SLAVE_MODE_EXT1
- TIM_SLAVE_MODE_GATED_RESET
- TIM_SLAVE_MODE_TRIG_RESET
return none
void TIM_SelectMasterSlaveMode(TIM_Module *TIMx, uint32_t TIM_MasterSlaveMode)Sets or Resets the TIMx Master/Slave Mode.
name TIM_SelectMasterSlaveMode
fun Sets or Resets the TIMx Master/Slave Mode.
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
- GTIM1
- GTIM2
- GTIM3
- GTIM4
param TIM_MasterSlaveMode
- TIM_MASTER_SLAVE_MODE_ENABLE
- TIM_MASTER_SLAVE_MODE_DISABLE
return none
void TIM_SelectHallSensor(TIM_Module *TIMx, FunctionalState Cmd)Enables or disables the TIMx’s Hall sensor interface.
name TIM_SelectHallSensor
fun Enables or disables the TIMx's Hall sensor interface.
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
- GTIM1
- GTIM2
- GTIM3
- GTIM4
param Cmd
- ENABLE
- DISABLE
return none
void TIM_ConfigDma(TIM_Module *TIMx, uint32_t TIM_DMABase, uint32_t TIM_DMABurstLength)Configures the TIMx’s DMA interface.
name TIM_ConfigDma
fun Configures the TIMx's DMA interface.
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
- GTIM1
- GTIM2
- GTIM3
- GTIM4
param TIM_DMABase:
- TIM_DMABASE_CTRL1
- TIM_DMABASE_CTRL2
- TIM_DMABASE_STS
- TIM_DMABASE_EVTGEN
- TIM_DMABASE_SMCTRL
- TIM_DMABASE_DMAINTEN
- TIM_DMABASE_CAPCMPMOD1
- TIM_DMABASE_CAPCMPMOD2
- TIM_DMABASE_CAPCMPMOD3
- TIM_DMABASE_CAPCMPEN
- TIM_DMABASE_CAPCMPDAT1
- TIM_DMABASE_CAPCMPDAT2
- TIM_DMABASE_CAPCMPDAT3
- TIM_DMABASE_CAPCMPDAT4
- TIM_DMABASE_CAPCMPDAT5
- TIM_DMABASE_CAPCMPDAT6
- TIM_DMABASE_PSC
- TIM_DMABASE_AR
- TIM_DMABASE_CNT
- TIM_DMABASE_REPCNT
- TIM_DMABASE_BKDT
- TIM_DMABASE_CAPCMPDAT7
- TIM_DMABASE_CAPCMPDAT8
- TIM_DMABASE_CAPCMPDAT9
- TIM_DMABASE_BKFR
- TIM_DMABASE_C1FILT
- TIM_DMABASE_C2FILT
- TIM_DMABASE_C3FILT
- TIM_DMABASE_C4FILT
- TIM_DMABASE_FILTO
- TIM_DMABASE_INSEL
- TIM_DMABASE_AF1
- TIM_DMABASE_ENCDAT
- TIM_DMABASE_ENCMCTRL
- TIM_DMABASE_ENCLVR
param TIM_DMABurstLength:
- This parameter can be one value between:
TIM_DMABURST_LENGTH_1TRANSFER and TIM_DMABURST_LENGTH_37TRANSFERS.
return none
void TIM_EnableDma(TIM_Module *TIMx, uint32_t TIM_DMASource, FunctionalState Cmd)Enables or disables the TIMx’s DMA Requests.
name TIM_EnableDma
fun Enables or disables the TIMx's DMA Requests.
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
- GTIM1
- GTIM2
- GTIM3
- GTIM4
param TIM_DMASource:
- TIM_DMA_CC1
- TIM_DMA_CC2
- TIM_DMA_CC3
- TIM_DMA_CC4
- TIM_DMA_UPDATE
- TIM_DMA_COM
- TIM_DMA_TRIG
param Cmd:
- DISABLE
- ENABLE
return none
void TIM_ConfigInt(TIM_Module *TIMx, uint32_t TIM_IT, FunctionalState Cmd)Enables or disables the specified TIM interrupts.
name TIM_ConfigInt
fun Enables or disables the specified TIM interrupts.
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
- GTIM1
- GTIM2
- GTIM3
- GTIM4
- BTIM1
- BTIM2
param TIM_IT:
- TIM_INT_CC1
- TIM_INT_CC2
- TIM_INT_CC3
- TIM_INT_CC4
- TIM_INT_CC5
- TIM_INT_CC6
- TIM_INT_CC7
- TIM_INT_CC8
- TIM_INT_CC9
- TIM_INT_C3LDCNT
- TIM_INT_UPDATE
- TIM_INT_TRIG
- TIM_INT_BREAK
- TIM_INT_COM
param Cmd :
- ENABLE
- DISABLE
return none
note TIM_INT_C3LDCNT is only for GTIM1 or GTIM2.
FlagStatus TIM_GetFlagStatus(const TIM_Module *TIMx, uint32_t TIM_FLAG)Checks whether the specified TIM flag is set or not.
name TIM_GetFlagStatus
fun Checks whether the specified TIM flag is set or not.
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
- GTIM1
- GTIM2
- GTIM3
- GTIM4
param TIM_FLAG :
- TIM_FLAG_CC1
- TIM_FLAG_CC2
- TIM_FLAG_CC3
- TIM_FLAG_CC4
- TIM_FLAG_CC5
- TIM_FLAG_CC6
- TIM_FLAG_CC7
- TIM_FLAG_CC8
- TIM_FLAG_CC9
- TIM_FLAG_CC1OF
- TIM_FLAG_CC2OF
- TIM_FLAG_CC3OF
- TIM_FLAG_CC4OF
- TIM_FLAG_UPDATE
- TIM_FLAG_COM
- TIM_FLAG_TRIG
- TIM_FLAG_BREAK
- TIM_FLAG_SYS_BREAK
- TIM_FLAG_LBKP
- TIM_FLAG_PBKP
- TIM_FLAG_COMP
- TIM_FLAG_IOM
- TIM_FLAG_CSSF
- TIM_FLAG_C3LDCNT
return The new state of TIM_FLAG (SET or RESET).
void TIM_ClearFlag(TIM_Module *TIMx, uint32_t TIM_FLAG)Clears the TIMx’s pending flags.
name TIM_ClearFlag
fun Clears the TIMx's pending flags.
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
- GTIM1
- GTIM2
- GTIM3
- GTIM4
param TIM_FLAG :
- TIM_FLAG_CC1
- TIM_FLAG_CC2
- TIM_FLAG_CC3
- TIM_FLAG_CC4
- TIM_FLAG_CC5
- TIM_FLAG_CC6
- TIM_FLAG_CC7
- TIM_FLAG_CC8
- TIM_FLAG_CC9
- TIM_FLAG_CC1OF
- TIM_FLAG_CC2OF
- TIM_FLAG_CC3OF
- TIM_FLAG_CC4OF
- TIM_FLAG_UPDATE
- TIM_FLAG_COM
- TIM_FLAG_TRIG
- TIM_FLAG_BREAK
- TIM_FLAG_SYS_BREAK
- TIM_FLAG_LBKP
- TIM_FLAG_PBKP
- TIM_FLAG_COMP
- TIM_FLAG_IOM
- TIM_FLAG_CSSF
- TIM_FLAG_C3LDCNT
return none.
Use note: The implementation writes ~TIM_FLAG to TIMx->STS, clearing the flags of the bits passed in while every other bit is written as 1.
INTStatus TIM_GetIntStatus(const TIM_Module *TIMx, uint32_t TIM_IT)Checks whether the TIM interrupt has occurred or not.
name TIM_GetIntStatus
fun Checks whether the TIM interrupt has occurred or not.
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
- GTIM1
- GTIM2
- GTIM3
- GTIM4
param TIM_IT :
- TIM_INT_UPDATE
- TIM_INT_CC1
- TIM_INT_CC2
- TIM_INT_CC3
- TIM_INT_CC4
- TIM_INT_CC5
- TIM_INT_CC6
- TIM_INT_CC7
- TIM_INT_CC7
- TIM_INT_CC8
- TIM_INT_CC9
- TIM_INT_C3LDCNT
- TIM_INT_COM
- TIM_INT_TRIG
- TIM_INT_BREAK
return The new state of the TIM_IT(SET or RESET).
void TIM_ClrIntPendingBit(TIM_Module *TIMx, uint32_t TIM_IT)Clears the TIMx’s interrupt pending bits.
name TIM_ClrIntPendingBit
fun Clears the TIMx's interrupt pending bits.
param TIMx (The input parameters must be the following values):
- ATIM1
- ATIM2
- GTIM1
- GTIM2
- GTIM3
- GTIM4
param TIM_IT :
- TIM_INT_UPDATE
- TIM_INT_CC1
- TIM_INT_CC2
- TIM_INT_CC3
- TIM_INT_CC4
- TIM_INT_CC5
- TIM_INT_CC6
- TIM_INT_CC7
- TIM_INT_CC8
- TIM_INT_CC9
- TIM_INT_C3LDCNT
- TIM_INT_COM
- TIM_INT_TRIG
- TIM_INT_BREAK
return none.
Use note: The implementation clears the corresponding bit in TIMx->STS through one branch per TIM_IT; interrupt sources other than TIM_INT_UPDATE, TIM_INT_CC1 to TIM_INT_CC9, TIM_INT_C3LDCNT, TIM_INT_COM, TIM_INT_TRIG and TIM_INT_BREAK take no action.
5.20.3 Demo descriptions
This section describes the 18 TIM examples, covering six-step commutation, complementary outputs with dead time and break, DMA and DMA burst transfers, external triggering, and cascaded synchronization on the advanced-control timer ATIM1, as well as gated counting, input capture, and output compare on the general-purpose timers GTIM.
5.20.3.1 6Steps Six-step commutation
Example directory: projects/n32g41x_EVAL/examples/TIM/6Steps/
Configure the system clock and the six complementary output pins of ATIM1→Configure the time base and three frozen output channels→Configure break and dead time and enable the COM interrupt and main output→Trigger one COM event every 100 ms with SysTick→Rewrite the output enables of the three channel pairs in the COM interrupt→Observe the six-step commutation waveform on an oscilloscope
| Item | Source analysis |
|---|---|
| Function | Outputs a six-step commutation waveform on ATIM1 CH1 to CH3 and their complementary channels CH1N to CH3N, switching to the next step every 100 ms when SysTick triggers a COM event; the sequence is AB, AC, BC, BA, CA, CB. |
| Source files | src/main.c: main, RCC_Configuration, NVIC_Configuration, GPIO_Configuration, SysTick_Configuration, and SetSysClockToPLL;inc/main.h: the TIMx, channel pin, alternate-function, and interrupt number macros;src/n32g41x_it.c: SysTick_Handler generates the COM event and TIMx_IRQHandler rewrites the channels by step;inc/n32g41x_it.h: interrupt declarations;readme.txt: function, environment, and usage;MDK-ARM/ and EWARM/: Keil and IAR projects. |
| Key configuration | Pins: CH1 to CH3 are PA8, PA9, and PA10 and CH1N to CH3N are PB13, PB14, and PB15, all GPIO_MODE_AF_PP;Alternate function: CH1 and CH2 are chip-dependent ( GPIO_AF2 on N32G412, GPIO_AF1 on N32G415) while CH3 and CH1N to CH3N are GPIO_AF2 and GPIO_AF5;Time base: Prescaler=0, Period=4095, ClkDiv=TIM_CLK_DIV1, RepetCnt=0;Channels: three channels in TIM_OCMODE_TIMING with Pulse 2047, 1023, and 511;Brake: OSSRState and OSSIState enabled, LOCKLevel=TIM_LOCK_LEVEL_OFF;Interrupt: COM preemption and sub priority 1, SysTick 0; Clock: HSE+PLL, SYSCLK and AHB 72 MHz, ATIM1 144 MHz. |
| Program and data path | main first calls SetSysClockToPLL(RCC_PLL_SRC_HSE, 72000000), then configures RCC, NVIC, GPIO, and SysTick, initializes the ATIM1 time base and the three TIM_OCMODE_TIMING channels, enables capture-compare preload, the COM interrupt, the counter, and the main output, and enters an empty loop.SysTick_Handler calls TIM_GenerateEvent(TIMx, TIM_EVT_SRC_COM) every 100 ms;TIMx_IRQHandler clears the COM flag and, by the value of step, rewrites the three channels, with step cycling from 1 to 6. |
| Main APIs | TIM_InitTimBaseStruct, TIM_InitTimeBase, TIM_InitOcStruct, TIM_InitOc1 to TIM_InitOc3, TIM_InitBkdtStruct, TIM_ConfigBkdt, TIM_ConfigInt, TIM_Enable, TIM_EnableCtrlPwmOutputs, TIM_GenerateEvent, TIM_SelectOcMode, TIM_EnableCapCmpCh, TIM_EnableCapCmpChN |
| Verification | Enter debug mode after building and observe the six ATIM1 outputs with an oscilloscope or logic analyzer; the commutation changes every 100 ms in the order AB, AC, BC, BA, CA, CB. |
| Use note | By default the PA9 and PA10 jumper caps on the board connect to the NSLINK virtual serial port; unplug them if these pins are not used as a serial port. Supported devices are N32G412x8L7, N32G412xBL7, N32G415x8L7, and N32G415xBL7; the toolchains are KEIL MDK-ARM 5.34 and IAR EWARM 8.50.1. |
Core-code walkthrough and porting
The example first puts the three complementary channel pairs into frozen output and then rewrites the output enables of each channel in the COM interrupt.
Data path: SysTick_Handler → TIM_GenerateEvent(TIMx, TIM_EVT_SRC_COM) → TIMx_IRQHandler branches on step → TIM_SelectOcMode, TIM_EnableCapCmpCh, and TIM_EnableCapCmpChN rewrite the main and complementary outputs of CH1 to CH3 → PA8 to PA10 and PB13 to PB15 output the six-step commutation waveform
1. Configure the time base and three frozen output channels. main sets the counter to count up with period 4095 and then configures three channels in TIM_OCMODE_TIMING whose compare values are halved in turn.
/* Time Base configuration */
TIM_InitTimBaseStruct(&TIM_TimeBaseStructure);
TIM_TimeBaseStructure.Prescaler = 0;
TIM_TimeBaseStructure.CounterMode = TIM_CNT_MODE_UP;
TIM_TimeBaseStructure.Period = 4095;
TIM_TimeBaseStructure.ClkDiv = TIM_CLK_DIV1;
TIM_TimeBaseStructure.RepetCnt = 0;
TIM_InitTimeBase(TIMx, &TIM_TimeBaseStructure);
TIM_OCInitStructure.OCMode = TIM_OCMODE_TIMING;
TIM_OCInitStructure.OutputState = TIM_OUTPUT_STATE_ENABLE;
TIM_OCInitStructure.OutputNState = TIM_OUTPUT_NSTATE_ENABLE;
TIM_OCInitStructure.Pulse = 2047;
TIM_OCInitStructure.OCPolarity = TIM_OC_POLARITY_HIGH;
TIM_OCInitStructure.OCNPolarity = TIM_OCN_POLARITY_HIGH;
TIM_OCInitStructure.OCIdleState = TIM_OC_IDLE_STATE_SET;
TIM_OCInitStructure.OCNIdleState = TIM_OCN_IDLE_STATE_SET;
TIM_InitOc1(TIMx, &TIM_OCInitStructure);
TIM_OCInitStructure.Pulse = 1023;
TIM_InitOc2(TIMx, &TIM_OCInitStructure);
TIM_OCInitStructure.Pulse = 511;
TIM_InitOc3(TIMx, &TIM_OCInitStructure);
When porting to another timer or channel, check the three Pulse values and channel numbers together, and update the output and complementary output enable bits accordingly.
2. Configure break and dead time and open the COM interrupt. TIM_ConfigBkdt enables the output idle states and automatic output, TIM_EnableCapCmpPreloadControl opens capture-compare preload, and the code then enables the COM interrupt, the counter, and the main output.
/* Automatic Output enable, Break, dead time and lock configuration */
TIM_InitBkdtStruct(&TIM_BDTRInitStructure);
TIM_BDTRInitStructure.OSSRState = TIM_OSSR_STATE_ENABLE;
TIM_BDTRInitStructure.OSSIState = TIM_OSSI_STATE_ENABLE;
TIM_BDTRInitStructure.LOCKLevel = TIM_LOCK_LEVEL_OFF;
TIM_BDTRInitStructure.AutomaticOutput = TIM_AUTO_OUTPUT_ENABLE;
TIM_ConfigBkdt(TIMx, &TIM_BDTRInitStructure);
TIM_EnableCapCmpPreloadControl(TIMx, ENABLE);
/* interrupt Enable */
TIM_ConfigInt(TIMx, TIM_INT_COM, ENABLE);
/* TIMx counter enable */
TIM_Enable(TIMx, ENABLE);
/* Main Output Enable */
TIM_EnableCtrlPwmOutputs(TIMx, ENABLE);
Without TIM_EnableCtrlPwmOutputs the channels output no waveform, so the commutation never reaches the pins.
3. Generate the COM event at a fixed rate with SysTick. SysTick_Configuration sets a 100 ms interrupt from SystemCoreClock / 10, and the handler only generates one COM event.
void SysTick_Handler(void)
{
/* Generate TIMx COM event by software */
TIM_GenerateEvent(TIMx, TIM_EVT_SRC_COM);
}
The commutation rate follows from this interrupt period; change the divider in SysTick_Configuration to change how long each step lasts.
4. Rewrite the three channel pairs in the COM interrupt. Each entry clears the COM flag and then, by the value of step, picks one branch that switches the output compare mode and toggles the main and complementary outputs channel by channel; after step 6 the state returns to step 1.
if (step == 1)
{
/* Next step: Step 2 Configuration */
/* Channel3 configuration */
TIM_EnableCapCmpCh(TIMx, TIM_CH_3, TIM_CAP_CMP_DISABLE);
TIM_EnableCapCmpChN(TIMx, TIM_CH_3, TIM_CAP_CMP_N_DISABLE);
/* Channel1 configuration */
TIM_SelectOcMode(TIMx, TIM_CH_1, TIM_OCMODE_PWM1);
TIM_EnableCapCmpCh(TIMx, TIM_CH_1, TIM_CAP_CMP_ENABLE);
TIM_EnableCapCmpChN(TIMx, TIM_CH_1, TIM_CAP_CMP_N_DISABLE);
/* Channel2 configuration */
TIM_SelectOcMode(TIMx, TIM_CH_2, TIM_OCMODE_PWM1);
TIM_EnableCapCmpCh(TIMx, TIM_CH_2, TIM_CAP_CMP_DISABLE);
TIM_EnableCapCmpChN(TIMx, TIM_CH_2, TIM_CAP_CMP_N_ENABLE);
step++;
}
else if (step == 6)
{
/* Next step: Step 1 Configuration */
/* Channel1 configuration */
TIM_SelectOcMode(TIMx, TIM_CH_1, TIM_OCMODE_PWM1);
TIM_EnableCapCmpCh(TIMx, TIM_CH_1, TIM_CAP_CMP_ENABLE);
TIM_EnableCapCmpChN(TIMx, TIM_CH_2, TIM_CAP_CMP_N_DISABLE);
/* Channel3 configuration */
TIM_SelectOcMode(TIMx, TIM_CH_3, TIM_OCMODE_PWM1);
TIM_EnableCapCmpCh(TIMx, TIM_CH_3, TIM_CAP_CMP_DISABLE);
TIM_EnableCapCmpChN(TIMx, TIM_CH_3, TIM_CAP_CMP_N_ENABLE);
/* Channel2 configuration */
TIM_EnableCapCmpCh(TIMx, TIM_CH_2, TIM_CAP_CMP_DISABLE);
TIM_EnableCapCmpChN(TIMx, TIM_CH_2, TIM_CAP_CMP_N_DISABLE);
step = 1;
}
In the step == 6 branch the comment says Channel1 while the second TIM_EnableCapCmpChN call passes TIM_CH_2; this is stated as the code fact. When editing the commutation table, keep these calls in step with the actual channel numbers.
Corresponding source files: src/main.c, src/n32g41x_it.c, inc/main.h
5.20.3.2 ATIM1_Synchro GTIM3 and GTIM4 gated by ATIM1
Example directory: projects/n32g41x_EVAL/examples/TIM/ATIM1_Synchro/
Configure the clocks and CH1 output pins of ATIM1, GTIM3, and GTIM4→Configure GTIM3 and GTIM4 as gated slaves with PWM1 output→Configure the ATIM1 time base and the PWM2 output of CH1→Select the ATIM1 update event as the trigger output→Enable the three counters and the main outputs→Observe the GTIM3 and GTIM4 waveforms under ATIM1 gating
| Item | Source analysis |
|---|---|
| Function | ATIM1 acts as the master timer, outputs PWM, and uses its update event as the trigger output; GTIM3 and GTIM4 count on their own periods, gated by the ATIM1 update event, and each outputs PWM. |
| Source files | src/main.c: main, RCC_Configuration, GPIO_Configuration;inc/main.h: the TIMx/TIMy/TIMz and channel pin and alternate-function macros;src/n32g41x_it.c and inc/n32g41x_it.h: interrupt handlers;readme.txt: function, environment, and usage;MDK-ARM/ and EWARM/: Keil and IAR projects. |
| Key configuration | Pins: ATIM1 CH1 is PA8, GTIM3 CH1 is PA6, and GTIM4 CH1 is PB0, all GPIO_MODE_AF_PP;Alternate function: ATIM1 is chip-dependent ( GPIO_AF2 on N32G412, GPIO_AF1 on N32G415) while GTIM3 and GTIM4 are GPIO_AF12;Time base: GTIM3 Period=2, GTIM4 Period=1, ATIM1 Period=255 with RepetCnt=4, all Prescaler=0;Channels: slaves in TIM_OCMODE_PWM1 with Pulse=1, ATIM1 in TIM_OCMODE_PWM2 with Pulse=127;Slave mode: GTIM3 and GTIM4 use TIM_SLAVE_MODE_GATED and input trigger TIM_TRIG_SEL_IN_TR0;Clock: HSI+PLL, 80 MHz on N32G412 and 96 MHz on N32G415. |
| Program and data path | main configures RCC and GPIO and sets the GTIM3, GTIM4, and ATIM1 time bases with the shared structure;it then sets the GTIM3 and GTIM4 CH1 outputs, gated slave mode and input trigger, and the ATIM1 time base with the CH1 PWM2 output, and calls TIM_SelectOutputTrig(ATIM1, TIM_TRGO_SRC_UPDATE);finally it enables the ATIM1, GTIM3, and GTIM4 counters and their main outputs. Each ATIM1 update event opens one gating window on CH1, and GTIM3 and GTIM4 count on their own periods inside it. |
| Main APIs | TIM_InitTimBaseStruct, TIM_InitTimeBase, TIM_InitOcStruct, TIM_InitOc1, TIM_SelectSlaveMode, TIM_SelectInputTrig, TIM_SelectOutputTrig, TIM_Enable, TIM_EnableCtrlPwmOutputs |
| Verification | Enter debug mode after building and observe ATIM1 CH1, GTIM3 CH1, and GTIM4 CH1 with an oscilloscope or logic analyzer; after startup the GTIM3 period is 15 times and the GTIM4 period 10 times that of ATIM1. |
| Use note | The two slaves share one TIM_TimeBaseStructure;the GTIM4 configuration changes only Period, so a full reassignment is required when editing.Supported devices are N32G412x8L7, N32G412xBL7, N32G415x8L7, and N32G415xBL7; the toolchains are KEIL MDK-ARM 5.34 and IAR EWARM 8.50.1. |
Core-code walkthrough and porting
The example configures the two gated slaves first and then feeds the ATIM1 update event to them as the trigger source.
Data path: ATIM1 update event → TIM_SelectOutputTrig(ATIM1, TIM_TRGO_SRC_UPDATE) → the TIM_TRIG_SEL_IN_TR0 inputs of GTIM3 and GTIM4 → counting on their own Period inside the gating window → PWM output on CH1
1. GTIM3 follows ATIM1 in gated slave mode. The shared structure first gives GTIM3 period 2 and PWM1 output, then sets the slave mode to gated with ITR0 as the input trigger.
/* GTIM3 Slave Configuration: PWM1 Mode */
TIM_InitTimBaseStruct(&TIM_TimeBaseStructure);
TIM_TimeBaseStructure.Period = 2;
TIM_TimeBaseStructure.Prescaler = 0;
TIM_TimeBaseStructure.ClkDiv = TIM_CLK_DIV1;
TIM_TimeBaseStructure.CounterMode = TIM_CNT_MODE_UP;
TIM_InitTimeBase(GTIM3, &TIM_TimeBaseStructure);
TIM_InitOcStruct(&TIM_OCInitStructure);
TIM_OCInitStructure.OCMode = TIM_OCMODE_PWM1;
TIM_OCInitStructure.OutputState = TIM_OUTPUT_STATE_ENABLE;
TIM_OCInitStructure.Pulse = 1;
TIM_InitOc1(GTIM3, &TIM_OCInitStructure);
/* Slave Mode selection: GTIM2 */
TIM_SelectSlaveMode(GTIM3, TIM_SLAVE_MODE_GATED);
TIM_SelectInputTrig(GTIM3, TIM_TRIG_SEL_IN_TR0);
The last two lines carry a comment that says GTIM2 although the code operates on GTIM3; this is stated as the code fact.
2. GTIM4 is configured the same way. The GTIM3 flow is repeated with Period changed to 1, and the gated slave mode and ITR0 trigger are applied to GTIM4.
/* GTIM4 Slave Configuration: PWM1 Mode */
TIM_TimeBaseStructure.Period = 1;
TIM_TimeBaseStructure.Prescaler = 0;
TIM_TimeBaseStructure.ClkDiv = TIM_CLK_DIV1;
TIM_TimeBaseStructure.CounterMode = TIM_CNT_MODE_UP;
TIM_InitTimeBase(GTIM4, &TIM_TimeBaseStructure);
TIM_OCInitStructure.OCMode = TIM_OCMODE_PWM1;
TIM_OCInitStructure.OutputState = TIM_OUTPUT_STATE_ENABLE;
TIM_OCInitStructure.Pulse = 1;
TIM_InitOc1(GTIM4, &TIM_OCInitStructure);
/* Slave Mode selection: GTIM3 */
TIM_SelectSlaveMode(GTIM4, TIM_SLAVE_MODE_GATED);
TIM_SelectInputTrig(GTIM4, TIM_TRIG_SEL_IN_TR0);
Here the comment says GTIM3 while the target is GTIM4; the period ratio of the two slaves is set by their own Period values.
3. ATIM1 acts as master and emits the update event. main configures ATIM1 as a PWM2 master with period 255 and repetition counter 4, then selects the update event as the trigger output.
/* ATIM1 Time Base configuration */
TIM_TimeBaseStructure.Prescaler = 0;
TIM_TimeBaseStructure.CounterMode = TIM_CNT_MODE_UP;
TIM_TimeBaseStructure.Period = 255;
TIM_TimeBaseStructure.ClkDiv = TIM_CLK_DIV1;
TIM_TimeBaseStructure.RepetCnt = 4;
TIM_InitTimeBase(ATIM1, &TIM_TimeBaseStructure);
/* Channel 1 Configuration in PWM mode */
TIM_OCInitStructure.OCMode = TIM_OCMODE_PWM2;
TIM_OCInitStructure.OutputState = TIM_OUTPUT_STATE_ENABLE;
TIM_OCInitStructure.OutputNState = TIM_OUTPUT_NSTATE_ENABLE;
TIM_OCInitStructure.Pulse = 127;
TIM_OCInitStructure.OCPolarity = TIM_OC_POLARITY_LOW;
TIM_OCInitStructure.OCNPolarity = TIM_OCN_POLARITY_LOW;
TIM_OCInitStructure.OCIdleState = TIM_OC_IDLE_STATE_SET;
TIM_OCInitStructure.OCNIdleState = TIM_OCN_IDLE_STATE_RESET;
TIM_InitOc1(ATIM1, &TIM_OCInitStructure);
/* Master Mode selection */
TIM_SelectOutputTrig(ATIM1, TIM_TRGO_SRC_UPDATE);
The gating window length follows from Period and RepetCnt together; check both values and the CH1 Pulse whenever the commutation period changes.
4. Enable the three counters and the main outputs. Each timer must be enabled separately and each main output opened individually; a missing one leaves its channel silent.
/* ATIM1 counter enable */
TIM_Enable(ATIM1, ENABLE);
/* TIM enable counter */
TIM_Enable(GTIM3, ENABLE);
TIM_Enable(GTIM4, ENABLE);
/* Main Output Enable */
TIM_EnableCtrlPwmOutputs(ATIM1, ENABLE);
TIM_EnableCtrlPwmOutputs(GTIM3, ENABLE);
TIM_EnableCtrlPwmOutputs(GTIM4, ENABLE);
Corresponding source files: src/main.c, inc/main.h
5.20.3.3 Cascade_Synchro Cascaded timers
Example directory: projects/n32g41x_EVAL/examples/TIM/Cascade_Synchro/
Configure the clocks and the three CH1 output pins of GTIM1 to GTIM3→Configure the three time bases and the PWM1 outputs→Make GTIM2 a gated slave of GTIM1 and forward its update event→Make GTIM3 a gated slave of GTIM2→Enable the three counters and the GTIM3 main output→Observe the three-stage divided gated waveform
| Item | Source analysis |
|---|---|
| Function | Three timers are chained: the GTIM1 update event gates GTIM2 and the GTIM2 update event gates GTIM3, each outputting PWM on its CH1 to form a progressively divided gated waveform. |
| Source files | src/main.c: main, RCC_Configuration, GPIO_Configuration;inc/main.h: the TIMx (GTIM1), TIMy (GTIM2), and TIMz (GTIM3) and channel pin and alternate-function macros;src/n32g41x_it.c and inc/n32g41x_it.h: interrupt handlers;readme.txt: function, environment, and usage;MDK-ARM/ and EWARM/: Keil and IAR projects. |
| Key configuration | Pins: GTIM1 CH1 is PA0 (GPIO_AF2), GTIM2 CH1 is PB4 (GPIO_AF8), and GTIM3 CH1 is PA6 (GPIO_AF12), all GPIO_MODE_AF_PP;Time base: GTIM1 Period=255 and GTIM2 and GTIM3 Period=3, all Prescaler=0;Channels: GTIM1 in TIM_OCMODE_PWM1 with Pulse=64, GTIM2 and GTIM3 in TIM_OCMODE_PWM1 with Pulse=1;Slave mode: GTIM2 and GTIM3 use TIM_SLAVE_MODE_GATED and input trigger TIM_TRIG_SEL_IN_TR2;Master and slave: GTIM1 and GTIM2 enabled with trigger output TIM_TRGO_SRC_UPDATE;Clock: HSI+PLL, 80 MHz on N32G412 and 96 MHz on N32G415. |
| Program and data path | main configures RCC and GPIO, initializes the GTIM1, GTIM2, and GTIM3 time bases in turn with the shared structure, then configures the GTIM1 CH1 output and the master trigger output;it then configures the GTIM2 and GTIM3 CH1 outputs, makes GTIM2 a gated slave that forwards its own update event, and makes GTIM3 a gated slave; finally it enables the GTIM2, GTIM1, and GTIM3 counters and opens only the GTIM3 main output. |
| Main APIs | TIM_InitTimBaseStruct, TIM_InitTimeBase, TIM_InitOcStruct, TIM_InitOc1, TIM_SelectMasterSlaveMode, TIM_SelectOutputTrig, TIM_SelectSlaveMode, TIM_SelectInputTrig, TIM_Enable, TIM_EnableCtrlPwmOutputs |
| Verification | Enter debug mode after building and observe PA0, PB4, and PA6 with an oscilloscope or logic analyzer; the GTIM2 frequency is 1/4 of GTIM1 and the GTIM3 frequency is 1/4 of GTIM2. |
| Use note | All three stages share one TIM_TimeBaseStructure and only Period changes per stage;only GTIM3 calls TIM_EnableCtrlPwmOutputs. Supported devices are N32G412x8L7, N32G412xBL7, N32G415x8L7, and N32G415xBL7;the toolchains are KEIL MDK-ARM 5.34 and IAR EWARM 8.50.1. |
Core-code walkthrough and porting
The example chains the three timers end to end so that each stage is gated by the update event of the previous one.
Data path: GTIM1 update event → gated counting of GTIM2 → GTIM2 update event → gated counting of GTIM3 → three CH1 outputs of progressively divided PWM
1. All three time bases are set at once. The shared structure first gives GTIM1 period 255 and then GTIM2 and GTIM3 period 3, producing a 1/4 division per stage.
/* Time Base configuration */
TIM_InitTimBaseStruct(&TIM_TimeBaseStructure);
TIM_TimeBaseStructure.Prescaler = 0;
TIM_TimeBaseStructure.CounterMode = TIM_CNT_MODE_UP;
TIM_TimeBaseStructure.Period = 255;
TIM_TimeBaseStructure.ClkDiv = TIM_CLK_DIV1;
TIM_InitTimeBase(TIMx, &TIM_TimeBaseStructure);
TIM_TimeBaseStructure.Period = 3;
TIM_InitTimeBase(TIMy, &TIM_TimeBaseStructure);
TIM_TimeBaseStructure.Period = 3;
TIM_InitTimeBase(TIMz, &TIM_TimeBaseStructure);
The division ratio is the ratio of Period + 1 between neighbouring stages; check the whole chain when changing one period.
2. GTIM1 is the master and routes its update event to the trigger output. main configures the GTIM1 CH1 output, enables master-slave mode, and selects the update event as TRGO.
/* Master Configuration in PWM1 Mode */
TIM_InitOcStruct(&TIM_OCInitStructure);
TIM_OCInitStructure.OCMode = TIM_OCMODE_PWM1;
TIM_OCInitStructure.OutputState = TIM_OUTPUT_STATE_ENABLE;
TIM_OCInitStructure.Pulse = 64;
TIM_OCInitStructure.OCPolarity = TIM_OC_POLARITY_HIGH;
TIM_InitOc1(TIMx, &TIM_OCInitStructure);
/* Select the Master Slave Mode */
TIM_SelectMasterSlaveMode(TIMx, TIM_MASTER_SLAVE_MODE_ENABLE);
/* Master Mode selection */
TIM_SelectOutputTrig(TIMx, TIM_TRGO_SRC_UPDATE);
The code comment names ITR1, while the actual input trigger selected in the next block is TIM_TRIG_SEL_IN_TR2.
3. GTIM2 becomes the middle stage. GTIM2 takes ITR2 as the gating input, also enables master-slave mode, and sends its own update event to the trigger output for GTIM3.
/* Slave Mode selection: TIMy */
TIM_SelectSlaveMode(TIMy, TIM_SLAVE_MODE_GATED);
TIM_SelectInputTrig(TIMy, TIM_TRIG_SEL_IN_TR2);
/* Select the Master Slave Mode */
TIM_SelectMasterSlaveMode(TIMy, TIM_MASTER_SLAVE_MODE_ENABLE);
/* Master Mode selection: TIMy */
TIM_SelectOutputTrig(TIMy, TIM_TRGO_SRC_UPDATE);
/* Slave Mode selection: TIMz */
TIM_SelectSlaveMode(TIMz, TIM_SLAVE_MODE_GATED);
TIM_SelectInputTrig(TIMz, TIM_TRIG_SEL_IN_TR2);
GTIM3 uses the same TIM_TRIG_SEL_IN_TR2 input trigger; this selection must match the TRGO definition of the previous stage when the cascade is edited.
4. Enable the counters and the main output. All three counters must be enabled, and only GTIM3 has its main output opened.
/* TIM enable counter */
TIM_Enable(TIMy, ENABLE);
TIM_Enable(TIMx, ENABLE);
TIM_Enable(TIMz, ENABLE);
TIM_EnableCtrlPwmOutputs(TIMz, ENABLE);
Corresponding source files: src/main.c, inc/main.h
5.20.3.4 ComplementarySignals Complementary signals with dead time
Example directory: projects/n32g41x_EVAL/examples/TIM/ComplementarySignals/
Configure the ATIM1 clock and the four complementary output pairs and the break input pin→Compute the period and four duty cycles from the clock frequency→Configure the four channels in PWM2 mode with complementary outputs→Configure dead time, break, and automatic output→Enable the counter and the main output→Pull PA6 high and observe the break effect on the waveform
| Item | Source analysis |
|---|---|
| Function | ATIM1 outputs four complementary PWM pairs with duty cycles of 50%, 25%, 12.5%, and 12.5%, inserts dead time, and enables active-high break with automatic output; pulling PA6 high removes the PWM. |
| Source files | src/main.c: main, RCC_Configuration, GPIO_Configuration, SetSysClockToPLL;inc/main.h: the TIMx, four output-pair, and break-pin alternate-function macros;src/n32g41x_it.c and inc/n32g41x_it.h: interrupt handlers;readme.txt: function, environment, and usage;MDK-ARM/ and EWARM/: Keil and IAR projects. |
| Key configuration | Pins: CH1 to CH4 are PA8, PA9, PA10, and PA11 and CH1N to CH4N are PB13, PB14, PB15, and PB2, all GPIO_MODE_AF_PP;Break input: PA6 uses GPIO_MODE_INPUT and GPIO_AF2;Alternate function: CH1 and CH2 are chip-dependent ( GPIO_AF2 on N32G412, GPIO_AF1 on N32G415) while CH3, CH4, and the complementary channels are GPIO_AF2 and GPIO_AF5;Time base: Prescaler=0, Period=(PllFreq/16000)-1;Channels: four channels in TIM_OCMODE_PWM2 with Pulse computed from the duty-cycle formula;Brake: DeadTime=10, BreakPolarity=TIM_BREAK_POLARITY_HIGH, AutomaticOutput enabled;Clock: HSE+PLL, SYSCLK and AHB 72 MHz, ATIM1 144 MHz. |
| Program and data path | main first calls SetSysClockToPLL(RCC_PLL_SRC_HSE, 72000000), configures RCC and GPIO, reads PllFreq with RCC_GetClocksFreqValue, and computes TimerPeriod and the four ChannelxPulse values;it then initializes the time base and the four PWM2 channels, configures break, dead time, and automatic output, calls TIM_BreakInputSourceEnable to enable the IO1 break source, and finally enables the counter and the main output. |
| Main APIs | SetSysClockToPLL, RCC_ConfigAtim1Clk, RCC_GetClocksFreqValue, TIM_InitTimBaseStruct, TIM_InitTimeBase, TIM_InitOcStruct, TIM_InitOc1 to TIM_InitOc4, TIM_InitBkdtStruct, TIM_ConfigBkdt, TIM_BreakInputSourceEnable, TIM_Enable, TIM_EnableCtrlPwmOutputs |
| Verification | Enter debug mode after building and observe the ATIM1 waveform with an oscilloscope or logic analyzer; four complementary PWM pairs are visible while PA6 is low, and the PWM disappears once PA6 is pulled high. |
| Use note | By default the PA9 and PA10 jumper caps on the board connect to the NSLINK virtual serial port; unplug them if these pins are not used as a serial port. Supported devices are N32G412x8L7, N32G412xBL7, N32G415x8L7, and N32G415xBL7; the toolchains are KEIL MDK-ARM 5.34 and IAR EWARM 8.50.1. |
Core-code walkthrough and porting
The example first derives the 16 kHz period and the four duty cycles from the PLL frequency and then configures the four complementary channels, dead time, and break.
Data path: RCC_GetClocksFreqValue reads PllFreq → TimerPeriod and ChannelxPulse → TIM_InitTimeBase, TIM_InitOc1 to TIM_InitOc4 write AR and CCDATx → TIM_ConfigBkdt sets dead time and break → PA8 to PA11, PB13 to PB15, and PB2 output four complementary waveforms
1. Derive the period and the four compare values from the PLL frequency. PllFreq is divided by the target frequency to get the AR value, and the four compare values follow from the duty-cycle formula.
RCC_GetClocksFreqValue(&RCC_ClocksStructure);
/* Compute the value to be set in AR register to generate signal frequency at 16KHz */
TimerPeriod = (RCC_ClocksStructure.PllFreq / 16000) - 1;
/* Compute CCDAT1 value to generate a duty cycle at 50% for channel 1 */
Channel1Pulse = (uint16_t)(((uint32_t)5 * (TimerPeriod - 1)) / 10);
/* Compute CCDAT2 value to generate a duty cycle at 25% for channel 2 */
Channel2Pulse = (uint16_t)(((uint32_t)25 * (TimerPeriod - 1)) / 100);
/* Compute CCDAT3 value to generate a duty cycle at 12.5% for channel 3 */
Channel3Pulse = (uint16_t)(((uint32_t)125 * (TimerPeriod - 1)) / 1000);
/* Compute CCDAT4 value to generate a duty cycle at 12.5% for channel 4 */
Channel4Pulse = (uint16_t)(((uint32_t)125 * (TimerPeriod - 1)) / 1000);
To change the output frequency change the divisor 16000; to change a duty cycle change the numerator of the matching ChannelxPulse, and the two 12.5% channels are channel 3 and channel 4.
2. Configure the four PWM2 channels with complementary outputs. The time base and the four channels share one structure, and only Pulse changes per channel.
/* Time Base configuration */
TIM_InitTimBaseStruct(&TIM_TimeBaseStructure);
TIM_TimeBaseStructure.Prescaler = 0;
TIM_TimeBaseStructure.CounterMode = TIM_CNT_MODE_UP;
TIM_TimeBaseStructure.Period = TimerPeriod;
TIM_TimeBaseStructure.ClkDiv = TIM_CLK_DIV1;
TIM_TimeBaseStructure.RepetCnt = 0;
TIM_InitTimeBase(TIMx, &TIM_TimeBaseStructure);
/* Channel 1, 2, 3 and 4 Configuration in PWM mode */
TIM_InitOcStruct(&TIM_OCInitStructure);
TIM_OCInitStructure.OCMode = TIM_OCMODE_PWM2;
TIM_OCInitStructure.OutputState = TIM_OUTPUT_STATE_ENABLE;
TIM_OCInitStructure.OutputNState = TIM_OUTPUT_NSTATE_ENABLE;
TIM_OCInitStructure.Pulse = Channel1Pulse;
TIM_OCInitStructure.OCPolarity = TIM_OC_POLARITY_LOW;
TIM_OCInitStructure.OCNPolarity = TIM_OCN_POLARITY_LOW;
TIM_OCInitStructure.OCIdleState = TIM_OC_IDLE_STATE_SET;
TIM_OCInitStructure.OCNIdleState = TIM_OCN_IDLE_STATE_RESET;
TIM_InitOc1(TIMx, &TIM_OCInitStructure);
TIM_OCInitStructure.Pulse = Channel2Pulse;
TIM_InitOc2(TIMx, &TIM_OCInitStructure);
TIM_OCInitStructure.Pulse = Channel3Pulse;
TIM_InitOc3(TIMx, &TIM_OCInitStructure);
TIM_OCInitStructure.Pulse = Channel4Pulse;
TIM_InitOc4(TIMx, &TIM_OCInitStructure);
OutputNState decides whether the complementary pins output; set it to TIM_OUTPUT_NSTATE_DISABLE for single-ended output.
3. Configure dead time and break. TIM_ConfigBkdt writes the dead time and break polarity, and TIM_BreakInputSourceEnable then enables IO1 as the break source.
/* Automatic Output enable, Break, dead time and lock configuration */
TIM_InitBkdtStruct(&TIM_BDTRInitStructure);
TIM_BDTRInitStructure.OSSRState = TIM_OSSR_STATE_ENABLE;
TIM_BDTRInitStructure.OSSIState = TIM_OSSI_STATE_ENABLE;
TIM_BDTRInitStructure.LOCKLevel = TIM_LOCK_LEVEL_OFF;
TIM_BDTRInitStructure.DeadTime = 10;
TIM_BDTRInitStructure.Break = TIM_BREAK_IN_ENABLE;
TIM_BDTRInitStructure.BreakPolarity = TIM_BREAK_POLARITY_HIGH;
TIM_BDTRInitStructure.AutomaticOutput = TIM_AUTO_OUTPUT_ENABLE;
TIM_ConfigBkdt(TIMx, &TIM_BDTRInitStructure);
TIM_BreakInputSourceEnable(TIMx, TIM_BREAK_IOM1, TIM_BREAK_SOURCE_POLARITY_NONINVERT, ENABLE);
The dead time length follows from DeadTime; BreakPolarity is active high, matching the readme behavior where pulling PA6 high removes the PWM.
4. Enable the counter and the main output. The break configuration only reaches the pins once the main output is enabled.
/* TIMx counter enable */
TIM_Enable(TIMx, ENABLE);
/* Main Output Enable */
TIM_EnableCtrlPwmOutputs(TIMx, ENABLE);
Corresponding source files: src/main.c, inc/main.h
5.20.3.5 DMA Update-event transfer
Example directory: projects/n32g41x_EVAL/examples/TIM/DMA/
Configure the ATIM1 and DMA clocks and the CH3 complementary output pin→Compute the channel period and three duty cycles from the system clock→Configure the CH3 complementary PWM output and the repetition counter→Configure DMA1_CH5 to transfer in circular mode to CCDAT3→Enable the update DMA request and the main output→Observe the duty cycle changing every 6 periods
| Item | Source analysis |
|---|---|
| Function | ATIM1 CH3 and CH3N output complementary PWM, and every 6 update events DMA1_CH5 transfers the next compare value from SRC_Buffer[3] to CCDAT3 in a circular manner, so the duty cycle cycles through 50%, 37.5%, and 25%. |
| Source files | src/main.c: main, RCC_Configuration, GPIO_Configuration, DMA_Configuration;inc/main.h: the TIMx, CH3, and CH3N pin and alternate-function macros;src/n32g41x_it.c and inc/n32g41x_it.h: interrupt handlers;readme.txt: function, environment, and usage;MDK-ARM/ and EWARM/: Keil and IAR projects. |
| Key configuration | Pins: CH3 is PA10 (GPIO_AF2) and CH3N is PB15 (GPIO_AF5), both GPIO_MODE_AF_PP;Time base: Prescaler=0, Period=(SystemCoreClock/80000)-1, ClkDiv=TIM_CLK_DIV1, RepetCnt=5;Channel: CH3 uses TIM_OCMODE_PWM2 with Pulse from SRC_Buffer[0] and polarity TIM_OC_POLARITY_LOW;DMA1_CH5: peripheral address &TIMx->CCDAT3, memory address SRC_Buffer, BufSize=3, direction DMA_DIR_PERIPH_DST, DMA_MODE_CIRCULAR, DMA_PRIORITY_HIGH, request DMA_REMAP_ATIM1_UP;Clock: HSI+PLL, 80 MHz on N32G412 and 96 MHz on N32G415. |
| Program and data path | main configures RCC, GPIO, and DMA, computes TimerPeriod and three duty cycles from SystemCoreClock into SRC_Buffer, initializes the time base (RepetCnt=5) and the CH3 complementary PWM output, enables the update DMA request, the main output, and the counter, and then enters an empty loop.Every 6 update events ATIM1 issues one DMA request, DMA1_CH5 writes CCDAT3 circularly, and the CH3 and CH3N duty cycles change accordingly. |
| Main APIs | TIM_InitTimBaseStruct, TIM_InitTimeBase, TIM_InitOcStruct, TIM_InitOc3, TIM_EnableDma, TIM_Enable, TIM_EnableCtrlPwmOutputs, DMA_DeInit, DMA_StructInit, DMA_Init, DMA_RequestRemap, DMA_EnableChannel |
| Verification | Enter debug mode after building and observe ATIM1 CH3 and CH3N with an oscilloscope or logic analyzer; the duty cycle changes every 6 periods, in the order 50%, 37.5%, 25%, and repeats. |
| Use note | By default the PA9 and PA10 jumper caps on the board connect to the NSLINK virtual serial port; unplug them if these pins are not used as a serial port. Supported devices are N32G412x8L7, N32G412xBL7, N32G415x8L7, and N32G415xBL7; the toolchains are KEIL MDK-ARM 5.34 and IAR EWARM 8.50.1. |
Core-code walkthrough and porting
The example lets the ATIM1 update event trigger DMA, writing the three duty cycles to CCDAT3 in turn.
Data path: SystemCoreClock → TimerPeriod and SRC_Buffer[3] → ATIM1 update event (every 6th) → TIM_DMA_UPDATE request → DMA1_CH5 writes CCDAT3 circularly → the CH3 and CH3N duty cycles change
1. First compute the period and the three duty cycles. SystemCoreClock is divided by 80 kHz to get the AR value, and the three compare values follow from the 50%, 37.5%, and 25% ratios.
/* Compute the value to be set in AR register to generate signal frequency at 80KHz */
TimerPeriod = (SystemCoreClock / 80000) - 1;
/* Compute CCDAT3 value to generate a duty cycle at 50% */
SRC_Buffer[0] = (uint16_t)(((uint32_t)5 * (TimerPeriod - 1)) / 10);
/* Compute CCDAT3 value to generate a duty cycle at 37.5% */
SRC_Buffer[1] = (uint16_t)(((uint32_t)375 * (TimerPeriod - 1)) / 1000);
/* Compute CCDAT3 value to generate a duty cycle at 25% */
SRC_Buffer[2] = (uint16_t)(((uint32_t)25 * (TimerPeriod - 1)) / 100);
To change the output frequency change the divisor 80000; to change a duty-cycle step change the SRC_Buffer fill ratio, keeping the array length in step with BufSize.
2. The repetition counter of the time base sets the transfer cadence. RepetCnt=5 makes the update DMA request fire once every 6 counting periods.
/* Time Base configuration */
TIM_InitTimBaseStruct(&TIM_TimeBaseStructure);
TIM_TimeBaseStructure.Prescaler = 0;
TIM_TimeBaseStructure.CounterMode = TIM_CNT_MODE_UP;
TIM_TimeBaseStructure.Period = TimerPeriod;
TIM_TimeBaseStructure.ClkDiv = TIM_CLK_DIV1;
TIM_TimeBaseStructure.RepetCnt = 5;
TIM_InitTimeBase(TIMx, &TIM_TimeBaseStructure);
The duty-cycle step interval follows from RepetCnt + 1, so changing this value also changes the step rate.
3. Configure the CH3 complementary output and open the update DMA request. The four channels share one structure, only CH3 is configured here, and the compare value comes from SRC_Buffer[0].
/* Channel 3 Configuration in PWM mode */
TIM_InitOcStruct(&TIM_OCInitStructure);
TIM_OCInitStructure.OCMode = TIM_OCMODE_PWM2;
TIM_OCInitStructure.OutputState = TIM_OUTPUT_STATE_ENABLE;
TIM_OCInitStructure.OutputNState = TIM_OUTPUT_NSTATE_ENABLE;
TIM_OCInitStructure.Pulse = SRC_Buffer[0];
TIM_OCInitStructure.OCPolarity = TIM_OC_POLARITY_LOW;
TIM_OCInitStructure.OCNPolarity = TIM_OCN_POLARITY_LOW;
TIM_OCInitStructure.OCIdleState = TIM_OC_IDLE_STATE_SET;
TIM_OCInitStructure.OCNIdleState = TIM_OCN_IDLE_STATE_RESET;
TIM_InitOc3(TIMx, &TIM_OCInitStructure);
/* TIMx Update DMA Request enable */
TIM_EnableDma(TIMx, TIM_DMA_UPDATE, ENABLE);
To use another channel, change the channel number of TIM_InitOc3, the CCDAT3 peripheral address in DMA_Configuration, and the DMA_RequestRemap request source together.
4. Configure DMA1_CH5 to transfer circularly to CCDAT3. With peripheral address no-increment and memory increment, the DMA writes a 3-word buffer circularly into the same register.
/* DMA Channel5 Config */
DMA_DeInit(DMA_CH5);
DMA_StructInit(&DMA_InitStructure);
DMA_InitStructure.PeriphAddr = (uint32_t)&TIMx->CCDAT3;
DMA_InitStructure.MemAddr = (uint32_t)SRC_Buffer;
DMA_InitStructure.Direction = DMA_DIR_PERIPH_DST;
DMA_InitStructure.BufSize = 3;
DMA_InitStructure.PeriphInc = DMA_PERIPH_INC_DISABLE;
DMA_InitStructure.DMA_MemoryInc = DMA_MEM_INC_ENABLE;
DMA_InitStructure.PeriphDataSize = DMA_PERIPH_DATA_SIZE_WORD;
DMA_InitStructure.MemDataSize = DMA_MemoryDataSize_Word;
DMA_InitStructure.CircularMode = DMA_MODE_CIRCULAR;
DMA_InitStructure.Priority = DMA_PRIORITY_HIGH;
DMA_InitStructure.Mem2Mem = DMA_M2M_DISABLE;
DMA_Init(DMA_CH5, &DMA_InitStructure);
DMA_RequestRemap(DMA_REMAP_ATIM1_UP, DMA, DMA_CH5, ENABLE);
/* DMA Channel5 enable */
DMA_EnableChannel(DMA_CH5, ENABLE);
5. Enable the counter and the main output. The DMA request is produced only while the counter runs, and the main output decides whether CH3 and CH3N drive the pins.
/* Main Output Enable */
TIM_EnableCtrlPwmOutputs(TIMx, ENABLE);
/* TIMx counter enable */
TIM_Enable(TIMx, ENABLE);
Corresponding source files: src/main.c, inc/main.h
5.20.3.6 DMABurst DMA burst transfer
Example directory: projects/n32g41x_EVAL/examples/TIM/DMABurst/
Configure the ATIM1 and DMA clocks and the CH1 output pin→Configure the CH1 PWM output and the DADDR burst length→Configure DMA1_CH5 to transfer 8 words in normal mode to DADDR→Enable the counter, main output, and DMA channel and wait for the transfer to finish→Observe the waveform with the new period and duty cycle→Set DmaAgain in debug mode to trigger another transfer
| Item | Source analysis |
|---|---|
| Function | ATIM1 CH1 outputs PWM, and after one counting period DMA1_CH5 writes 8 words from SRC_Buffer[8] as a burst to the consecutive registers based at CCDAT1, changing the period, duty cycle, and repetition counter at the same time. |
| Source files | src/main.c: main, RCC_Configuration, GPIO_Configuration, DMA_Configuration;inc/main.h: the TIMx, CH1 pin, and alternate-function macros;src/n32g41x_it.c and inc/n32g41x_it.h: interrupt handlers;readme.txt: function, environment, and usage;MDK-ARM/ and EWARM/: Keil and IAR projects. |
| Key configuration | Pins: CH1 is PA8 in GPIO_MODE_AF_PP, chip-dependent (GPIO_AF2 on N32G412, GPIO_AF1 on N32G415);Time base: Period=0xFFFF;Channel: CH1 uses TIM_OCMODE_PWM1, OutputState=TIM_OUTPUT_STATE_ENABLE, Pulse=0x8FFF;Burst: TIM_ConfigDma(TIMx, TIM_DMABASE_CAPCMPDAT1, TIM_DMABURST_LENGTH_8TRANSFERS) with source array SRC_Buffer[8] first and last values 0x8FF/0xFFF;DMA1_CH5: peripheral address &TIMx->DADDR, BufSize=8, DMA_MODE_NORMAL, DMA_PRIORITY_HIGH;Clock: HSI+PLL, 80 MHz on N32G412 and 96 MHz on N32G415. |
| Program and data path | main configures RCC, GPIO, and DMA, initializes the time base and the CH1 PWM output, calls TIM_ConfigDma to set the burst base and length and enables the update DMA request, then enables the counter, the main output, and the DMA channel, and waits for the transfer to finish with DMA_GetFlagStatus(DMA_FLAG_TC5, DMA) before clearing the flag;in the main loop, when DmaAgain is set, it reconfigures the burst and DMA and waits for the transfer to complete again. |
| Main APIs | TIM_InitTimBaseStruct, TIM_InitTimeBase, TIM_InitOcStruct, TIM_InitOc1, TIM_ConfigDma, TIM_EnableDma, TIM_Enable, TIM_EnableCtrlPwmOutputs, DMA_DeInit, DMA_StructInit, DMA_Init, DMA_RequestRemap, DMA_EnableChannel, DMA_GetFlagStatus, DMA_ClearFlag |
| Verification | Enter debug mode after building and observe ATIM1 CH1 with an oscilloscope or logic analyzer; after the first period the waveform takes on the new period and duty cycle written by DMA. In debug mode, setting DmaAgain to 1 transfers the 8 words to the TIM1 DMA registers again. |
| Use note | By default the PA9 and PA10 jumper caps on the board connect to the NSLINK virtual serial port; unplug them if these pins are not used as a serial port. Supported devices are N32G412x8L7, N32G412xBL7, N32G415x8L7, and N32G415xBL7; the toolchains are KEIL MDK-ARM 5.34 and IAR EWARM 8.50.1. |
Core-code walkthrough and porting
The example uses a DMA burst to write a whole group of register parameters at once, so that the period and duty cycle both change after one period.
Data path: SRC_Buffer[8] → ATIM1 update event → TIM_DMA_UPDATE request → DMA1_CH5 bursts 8 words based at DADDR → CCDAT1 to CCDAT6, PSC, and AR update → CH1 outputs the new period and duty cycle
1. Configure the time base and the CH1 initial value. main sets the period to 0xFFFF and CH1 outputs PWM with Pulse=0x8FFF, waiting for DMA to rewrite it.
TIM_InitTimBaseStruct(&TIM_TimeBaseStructure);
TIM_TimeBaseStructure.Period = 0xFFFF;
TIM_TimeBaseStructure.Prescaler = 0;
TIM_TimeBaseStructure.ClkDiv = TIM_CLK_DIV1;
TIM_TimeBaseStructure.CounterMode = TIM_CNT_MODE_UP;
TIM_InitTimeBase(TIMx, &TIM_TimeBaseStructure);
/* TIM Configuration in PWM Mode */
TIM_InitOcStruct(&TIM_OCInitStructure);
TIM_OCInitStructure.OCMode = TIM_OCMODE_PWM1;
TIM_OCInitStructure.OutputState = TIM_OUTPUT_STATE_ENABLE;
TIM_OCInitStructure.Pulse = 0x8FFF;
TIM_InitOc1(TIMx, &TIM_OCInitStructure);
The first and eighth elements of SRC_Buffer write the registers tied to the start and end of the period while the rest stay 0; maintain these 8 words in burst-write order when the parameters change.
2. Open the burst transfer and the update DMA request and wait. TIM_ConfigDma sets a burst of 8 transfers based at CCDAT1; the code then enables the peripherals and waits for the transfer to finish.
/* TIMx DADDR Base register and DMA Burst Length Config */
TIM_ConfigDma(TIMx, TIM_DMABASE_CAPCMPDAT1, TIM_DMABURST_LENGTH_8TRANSFERS);
/* TIMx DMA Update enable */
TIM_EnableDma(TIMx, TIM_DMA_UPDATE, ENABLE);
/* TIMx enable */
TIM_Enable(TIMx, ENABLE);
/* TIMx PWM Outputs Enable */
TIM_EnableCtrlPwmOutputs(TIMx, ENABLE);
/* DMA Channel5 enable */
DMA_EnableChannel(DMA_CH5, ENABLE);
/* Wait until DMA Channel5 end of Transfer */
while (!DMA_GetFlagStatus(DMA_FLAG_TC5, DMA))
{
}
The burst base and length must match the peripheral address and BufSize in DMA_Configuration, otherwise the number of registers written will differ from the intent.
3. DMA1_CH5 transfers to DADDR in normal mode. With peripheral address no-increment and memory increment, the DMA writes the 8 words in turn to the burst base register.
/* DMA Channel5 Config */
DMA_DeInit(DMA_CH5);
DMA_StructInit(&DMA_InitStructure);
DMA_InitStructure.PeriphAddr = (uint32_t)&TIMx->DADDR;
DMA_InitStructure.MemAddr = (uint32_t)SRC_Buffer;
DMA_InitStructure.Direction = DMA_DIR_PERIPH_DST;
DMA_InitStructure.BufSize = 8;
DMA_InitStructure.PeriphInc = DMA_PERIPH_INC_DISABLE;
DMA_InitStructure.DMA_MemoryInc = DMA_MEM_INC_ENABLE;
DMA_InitStructure.PeriphDataSize = DMA_PERIPH_DATA_SIZE_WORD;
DMA_InitStructure.MemDataSize = DMA_MemoryDataSize_Word;
DMA_InitStructure.CircularMode = DMA_MODE_NORMAL;
DMA_InitStructure.Priority = DMA_PRIORITY_HIGH;
DMA_InitStructure.Mem2Mem = DMA_M2M_DISABLE;
DMA_Init(DMA_CH5, &DMA_InitStructure);
DMA_RequestRemap(DMA_REMAP_ATIM1_UP, DMA, DMA_CH5, ENABLE);
This uses DMA_MODE_NORMAL, so the transfer stops once done; a further transfer needs DmaAgain to reconfigure and restart the channel.
4. Use DmaAgain to trigger another transfer. When the main loop sees DmaAgain non-zero it clears the flag, reconfigures the burst and DMA, enables the channel, and waits for the transfer to finish again.
if (DmaAgain)
{
DmaAgain = 0;
TIM_ConfigDma(TIMx, TIM_DMABASE_CAPCMPDAT1, TIM_DMABURST_LENGTH_8TRANSFERS);
TIM_EnableDma(TIMx, TIM_DMA_UPDATE, ENABLE);
DMA_Configuration();
/* DMA Channel5 enable */
DMA_EnableChannel(DMA_CH5, ENABLE);
Corresponding source files: src/main.c, inc/main.h
5.20.3.7 ExtTrigger_Synchro External trigger synchronization
Example directory: projects/n32g41x_EVAL/examples/TIM/ExtTrigger_Synchro/
Configure the clocks and the output and input pins of ATIM1, GTIM2, and GTIM3→Configure the ATIM1 CH1 toggle output and the CH2 input capture→Set ATIM1 to TI2 gated slave mode and route its enable event to the trigger output→Configure GTIM2 and GTIM3 as gated slaves in turn→Enable the three counters and the main outputs→Drive PA9 high and low and observe the timers starting and stopping
| Item | Source analysis |
|---|---|
| Function | ATIM1 CH2 acts as an external trigger input; TI2 gates ATIM1 itself and in turn gates GTIM2 and GTIM3, and all three timers output a toggle waveform on CH1, counting while the external trigger is high and stopping while it is low. |
| Source files | src/main.c: main, RCC_Configuration, GPIO_Configuration;inc/main.h: the TIMx (ATIM1), TIMy (GTIM2), and TIMz (GTIM3) and channel pin and alternate-function macros;src/n32g41x_it.c and inc/n32g41x_it.h: interrupt handlers;readme.txt: function, environment, and usage;MDK-ARM/ and EWARM/: Keil and IAR projects. |
| Key configuration | Pins: ATIM1 CH1 is PA8 and CH2 is PA9, GTIM2 CH1 is PB4 (GPIO_AF8), and GTIM3 CH1 is PA6 (GPIO_AF12);ATIM1 CH1 is GPIO_MODE_AF_PP and CH2 is GPIO_MODE_INPUT;Time base: all three use Period=73;Channels: all three use TIM_OCMODE_TOGGLE, with ATIM1 CH1 Pulse=64;Capture: CH2 rising-edge direct capture; Trigger: ATIM1 uses TIM_TRIG_SEL_TI2FP2 gating and GTIM2 and GTIM3 use TIM_TRIG_SEL_IN_TR0 and TIM_TRIG_SEL_IN_TR2, all TIM_SLAVE_MODE_GATED;Trigger output: ATIM1 and GTIM2 use TIM_TRGO_SRC_ENABLE;Clock: HSI+PLL, 80 MHz on N32G412 and 96 MHz on N32G415. |
| Program and data path | main configures RCC and GPIO and sets all three time bases (ATIM1, GTIM2, GTIM3) to period 73 and prescaler 3 with the shared structure;it then configures the ATIM1 CH1 toggle output, the CH2 input capture, TI2 gated slave mode, and the enable-event trigger output; it makes GTIM2 an ITR0 gated slave that forwards the enable event and GTIM3 an ITR2 gated slave; finally it enables the ATIM1 and GTIM3 main outputs and all three counters. |
| Main APIs | TIM_InitTimBaseStruct, TIM_InitTimeBase, TIM_InitOcStruct, TIM_InitOc1, TIM_InitIcStruct, TIM_ICInit, TIM_SelectInputTrig, TIM_SelectSlaveMode, TIM_SelectMasterSlaveMode, TIM_SelectOutputTrig, TIM_Enable, TIM_EnableCtrlPwmOutputs |
| Verification | Enter debug mode after building and observe ATIM1 CH1, GTIM2 CH1, and GTIM3 CH1 with an oscilloscope or logic analyzer; the timers count while ATIM1 CH2 is high and stop while it is low. |
| Use note | By default the PA9 and PA10 jumper caps on the board connect to the NSLINK virtual serial port; unplug them if PA9 is not used as a serial input. Supported devices are N32G412x8L7, N32G412xBL7, N32G415x8L7, and N32G415xBL7; the toolchains are KEIL MDK-ARM 5.34 and IAR EWARM 8.50.1. |
Core-code walkthrough and porting
The example treats the ATIM1 CH2 pin as an external trigger and uses its level to control the start and stop of all three counters at once.
Data path: PA9 (TI2) level → TIM_SelectInputTrig(TIMx, TIM_TRIG_SEL_TI2FP2) gates ATIM1 → ATIM1 enable event → GTIM2 gated counting → GTIM2 enable event → GTIM3 gated counting → three CH1 toggle outputs
1. The three time bases and the toggle output. The shared structure sets all three timers to period 73 and prescaler 3, and the ATIM1 CH1 outputs in toggle mode.
/* Time base configuration */
TIM_InitTimBaseStruct(&TIM_TimeBaseStructure);
TIM_TimeBaseStructure.Period = 73;
TIM_TimeBaseStructure.Prescaler = 3;
TIM_TimeBaseStructure.ClkDiv = TIM_CLK_DIV1;
TIM_TimeBaseStructure.CounterMode = TIM_CNT_MODE_UP;
TIM_InitTimeBase(TIMx, &TIM_TimeBaseStructure);
TIM_TimeBaseStructure.Period = 73;
TIM_InitTimeBase(TIMy, &TIM_TimeBaseStructure);
TIM_TimeBaseStructure.Period = 73;
TIM_InitTimeBase(TIMz, &TIM_TimeBaseStructure);
/* Master Configuration in Toggle Mode */
TIM_InitOcStruct(&TIM_OCInitStructure);
TIM_OCInitStructure.OCMode = TIM_OCMODE_TOGGLE;
TIM_OCInitStructure.OutputState = TIM_OUTPUT_STATE_ENABLE;
TIM_OCInitStructure.Pulse = 64;
TIM_OCInitStructure.OCPolarity = TIM_OC_POLARITY_HIGH;
TIM_InitOc1(TIMx, &TIM_OCInitStructure);
The toggle threshold falls on the compare value, so changing Period and Pulse changes both the output frequency and the duty cycle, and all three timers share the same starting values.
2. Configure the CH2 input capture and treat TI2 as the gating trigger. CH2 captures the rising edge, the input trigger selects TI2FP2, the slave mode is set to gated, and the enable event is routed to the trigger output.
/* TIMx Input Capture Configuration */
TIM_InitIcStruct(&TIM_ICInitStructure);
TIM_ICInitStructure.Channel = TIM_CH_2;
TIM_ICInitStructure.ICPolarity = TIM_IC_POLARITY_RISING;
TIM_ICInitStructure.ICSelection = TIM_IC_SELECTION_DIRECTTI;
TIM_ICInitStructure.ICPrescaler = TIM_IC_PSC_DIV1;
TIM_ICInitStructure.ICFilter = 0;
TIM_ICInit(TIMx, &TIM_ICInitStructure);
/* TIMx Input trigger configuration: External Trigger connected to TI2 */
TIM_SelectInputTrig(TIMx, TIM_TRIG_SEL_TI2FP2);
TIM_SelectSlaveMode(TIMx, TIM_SLAVE_MODE_GATED);
/* Select the Master Slave Mode */
TIM_SelectMasterSlaveMode(TIMx, TIM_MASTER_SLAVE_MODE_ENABLE);
/* Master Mode selection: TIMx */
TIM_SelectOutputTrig(TIMx, TIM_TRGO_SRC_ENABLE);
To change the trigger polarity change ICPolarity; to move the external trigger pin, the input trigger selection must move to the matching TI mapping as well.
3. GTIM2 and GTIM3 are gated stage by stage. GTIM2 is gated by ITR0 and forwards the enable event, and GTIM3 is gated by ITR2, forming the chain from the external trigger to the two slave timers.
/* Slave Mode selection: TIMy */
TIM_SelectInputTrig(TIMy, TIM_TRIG_SEL_IN_TR0);
TIM_SelectSlaveMode(TIMy, TIM_SLAVE_MODE_GATED);
/* Select the Master Slave Mode */
TIM_SelectMasterSlaveMode(TIMy, TIM_MASTER_SLAVE_MODE_ENABLE);
/* Master Mode selection: TIMy */
TIM_SelectOutputTrig(TIMy, TIM_TRGO_SRC_ENABLE);
/* Slave Mode selection: TIMz */
TIM_SelectInputTrig(TIMz, TIM_TRIG_SEL_IN_TR2);
TIM_SelectSlaveMode(TIMz, TIM_SLAVE_MODE_GATED);
The input triggers of the two slaves must match the ITR number of the previous stage, so the whole chain needs to be checked together when the cascade is edited.
4. Enable the main outputs and the counters. Only ATIM1 and GTIM3 have their main outputs opened, and the three counters must each be enabled.
/* TIMx Main Output Enable */
TIM_EnableCtrlPwmOutputs(TIMx, ENABLE);
/* TIMz Main Output Enable */
TIM_EnableCtrlPwmOutputs(TIMz, ENABLE);
/* TIM enable counter */
TIM_Enable(TIMx, ENABLE);
TIM_Enable(TIMy, ENABLE);
TIM_Enable(TIMz, ENABLE);
Corresponding source files: src/main.c, inc/main.h
5.20.3.8 InputCapture Input capture frequency measurement
Example directory: projects/n32g41x_EVAL/examples/TIM/InputCapture/
Configure the GTIM1 clock and the CH2 input and PA3 output pins→Configure CH2 for rising-edge direct capture and open the CC2 interrupt→Enable the counter and let the main loop wait for the test pulse→Generate two rising edges on PA3→The CC2 interrupt records both capture values and computes the frequency→Read the measured frequency value in the watch window
| Item | Source analysis |
|---|---|
| Function | GTIM1 CH2 measures the frequency of an external signal by rising-edge input capture; the example generates a test pulse on PA3 wired to PA1, and TIMxFreq follows from the reciprocal of the difference between two capture values. |
| Source files | src/main.c: main, RCC_Configuration, GPIO_Configuration, NVIC_Configuration, GenTwoRisingEdge;inc/main.h: the TIMx (GTIM1), CH2 pin, alternate-function, and interrupt number macros;src/n32g41x_it.c: TIMx_IRQHandler performs both captures and computes the frequency;inc/n32g41x_it.h: interrupt declarations;readme.txt: function, environment, and usage;MDK-ARM/ and EWARM/: Keil and IAR projects. |
| Key configuration | GTIM1 CH2 is PA1 (GPIO_AF2) and PA3 is a test-pulse output in GPIO_MODE_OUTPUT_PP. The input capture uses Channel=TIM_CH_2, ICPolarity=TIM_IC_POLARITY_RISING, ICSelection=TIM_IC_SELECTION_DIRECTTI, ICPrescaler=TIM_IC_PSC_DIV1, and ICFilter=0x0;the interrupt is opened by TIM_ConfigInt(TIMx, TIM_INT_CC2, ENABLE), and TIMx_IRQHandler has preemption priority 1 and sub priority 0.GenTwoRisingEdge is triggered by the variable gOnePulsEn and uses GPIO_SetBits and GPIO_ResetBits to produce two rising edges on PA3.The clock is HSI+PLL: 80 MHz on N32G412 and 96 MHz on N32G415. |
| Program and data path | main configures RCC, GPIO, and NVIC, initializes the CH2 input capture, clears the update and CC2 flags and opens the CC2 interrupt, enables the counter, and enters a main loop that repeatedly calls GenTwoRisingEdge. After gOnePulsEn is set to 1 in debug mode, PA3 produces two rising edges and TIMx_IRQHandler reads TIM_GetCap2(TIMx) into IC3ReadValue1 and IC3ReadValue2 in the two CC2 interrupts, computes Capture from the difference, and gets TIMxFreq = SystemCoreClock / cap. |
| Main APIs | TIM_InitIcStruct, TIM_ICInit, TIM_ClrIntPendingBit, TIM_ConfigInt, TIM_Enable, TIM_GetIntStatus, TIM_GetCap2, GPIO_InitStruct, GPIO_InitPeripheral, GPIO_SetBits, GPIO_ResetBits |
| Verification | Enter debug mode after building, connect PA3 to PA1, and add TIMxFreq to the watch window;set gOnePulsEn to 1 in the debug window, PA3 toggles, and the TIMxFreq value can then be read. |
| Use note | PA3 and PA1 must be wired together for the test, otherwise no pulse is captured. By default the PA9 and PA10 jumper caps on the board connect to the NSLINK virtual serial port; unplug them if they are not used as a serial port. Supported devices are N32G412x8L7, N32G412xBL7, N32G415x8L7, and N32G415xBL7; the toolchains are KEIL MDK-ARM 5.34 and IAR EWARM 8.50.1. |
Core-code walkthrough and porting
The example infers the input frequency from the count difference between two rising-edge captures, with the test pulse produced by an IO of the same chip.
Data path: gOnePulsEn → GenTwoRisingEdge → PA3 produces two rising edges → the CH2 capture configured by TIM_ICInit → TIMx_IRQHandler reads TIM_GetCap2 → Capture and TIMxFreq
1. Configure the CH2 rising-edge capture and open the CC2 interrupt. After setting the capture channel, polarity, selection, and filter, the code clears the flags, opens the CC2 interrupt, and enables the counter.
TIM_InitIcStruct(&TIM_ICInitStructure);
TIM_ICInitStructure.Channel = TIM_CH_2;
TIM_ICInitStructure.ICPolarity = TIM_IC_POLARITY_RISING;
TIM_ICInitStructure.ICSelection = TIM_IC_SELECTION_DIRECTTI;
TIM_ICInitStructure.ICPrescaler = TIM_IC_PSC_DIV1;
TIM_ICInitStructure.ICFilter = 0x0;
TIM_ICInit(TIMx, &TIM_ICInitStructure);
TIM_ClrIntPendingBit(TIMx, TIM_INT_UPDATE);
TIM_ClrIntPendingBit(TIMx, TIM_INT_CC2);
/* Enable the CC2 Interrupt Request */
TIM_ConfigInt(TIMx, TIM_INT_CC2, ENABLE);
/* TIM enable counter */
TIM_Enable(TIMx, ENABLE);
Changing the capture polarity or prescaler directly changes the premise of the TIMxFreq computation, and a non-zero ICFilter also introduces a fixed filtering delay.
2. Generate the test pulse on PA3. When gOnePulsEn is non-zero, GenTwoRisingEdge clears the flag and drives PA3 high then low, repeating twice to form two rising edges.
if (gOnePulsEn)
{
gOnePulsEn = 0;
GPIO_SetBits(GPIOA, GPIO_PIN_3);
{
volatile uint32_t i = 0;
while (i++ < 10)
;
}
GPIO_ResetBits(GPIOA, GPIO_PIN_3);
The software delay between the two rising edges sets the order of magnitude of the measured frequency; this pulse-generation code can be removed when an external source is used.
3. Record the first capture value in the interrupt. The CC2 interrupt clears the flag first, and when CaptureNumber is 0 it saves the first capture value and sets the state.
if (TIM_GetIntStatus(TIMx, TIM_INT_CC2) == SET)
{
TIMxEnterIrqCnt++;
/* Clear TIMx Capture compare interrupt pending bit */
TIM_ClrIntPendingBit(TIMx, TIM_INT_CC2);
if (CaptureNumber == 0)
{
/* Get the Input Capture value */
IC3ReadValue1 = TIM_GetCap2(TIMx);
CaptureNumber = 1;
}
4. Compute the frequency after the second capture. On the second interrupt entry the code reads IC3ReadValue2, computes the difference according to the relation between the two capture values, and divides the system clock by the difference to get the frequency.
/* Capture computation */
if (val2 > val1)
{
cap = (val2 - val1);
}
else
{
cap = ((0xFFFF - val1) + val2);
}
Capture = cap;
/* Frequency computation */
TIMxFreq = SystemCoreClock / cap;
CaptureNumber = 0;
TIMxFreq is the quotient of the system clock and the count difference, so the result must be recalibrated after a change of the core clock or of Prescaler.
Corresponding source files: src/main.c, src/n32g41x_it.c, inc/main.h
5.20.3.9 OCActive Output compare active level
Example directory: projects/n32g41x_EVAL/examples/TIM/OCActive/
Configure the GTIM1 clock and the CH1 to CH4 output pins→Compute the 2 kHz counting-clock prescaler from the system clock→Configure the four channels in output compare Active mode with their compare values→Disable the preload of every channel and enable the AR preload→Enable the counter→Observe the four channels going to the active level in turn
| Item | Source analysis |
|---|---|
| Function | GTIM1 CH1 to CH4 are configured in output compare Active mode; when the count reaches each CCDATx the matching channel goes to the active level, with the four compare values at 1000, 500, 250, and 125 so the outputs transition in turn. |
| Source files | src/main.c: main, RCC_Configuration, GPIO_Configuration;inc/main.h: the TIMx (GTIM1), CH1 to CH4 pin, and alternate-function macros;src/n32g41x_it.c and inc/n32g41x_it.h: interrupt handlers;readme.txt: function, environment, and usage;MDK-ARM/ and EWARM/: Keil and IAR projects. |
| Key configuration | Pins: CH1 to CH4 are PA0, PA1, PA2, and PA3, all GPIO_MODE_AF_PP with GPIO_AF2;Time base: Period=65535, Prescaler=(SystemCoreClock/2000)-1, ClkDiv=TIM_CLK_DIV1, CounterMode=TIM_CNT_MODE_UP;Channels: four channels in OCMode=TIM_OCMODE_ACTIVE, OutputState=TIM_OUTPUT_STATE_ENABLE, polarity TIM_OC_POLARITY_HIGH, Pulse of 1000, 500, 250, and 125;Preload: per-channel preload disabled ( TIM_OC_PRE_LOAD_DISABLE) and AR preload enabled;Clock: HSI+PLL, 80 MHz on N32G412 and 96 MHz on N32G415. |
| Program and data path | main configures RCC and GPIO and computes PrescalerValue, initializes the time base and configures the output compare Active mode and preload of CH1, then repeats the same configuration for CH2, CH3, and CH4 with their own CCRx_Val, opens the AR preload, and finally enables the counter and enters an empty loop.As the count rises from 0 to 125, 250, 500, and 1000, CH4, CH3, CH2, and CH1 go to the active level in turn. |
| Main APIs | TIM_InitTimBaseStruct, TIM_InitTimeBase, TIM_InitOcStruct, TIM_InitOc1, TIM_InitOc2, TIM_InitOc3, TIM_InitOc4, TIM_ConfigOc1Preload, TIM_ConfigOc2Preload, TIM_ConfigOc3Preload, TIM_ConfigOc4Preload, TIM_ConfigArPreload, TIM_Enable |
| Verification | Enter debug mode after building and observe GTIM1 CH1 to CH4 with an oscilloscope or logic analyzer; when the count reaches CC1, CC2, CC3, and CC4 the matching channel goes to the active level. |
| Use note | By default the PA9 and PA10 jumper caps on the board connect to the NSLINK virtual serial port; unplug them if these pins are not used as a serial port. Supported devices are N32G412x8L7, N32G412xBL7, N32G415x8L7, and N32G415xBL7; the toolchains are KEIL MDK-ARM 5.34 and IAR EWARM 8.50.1. |
Core-code walkthrough and porting
The example lowers the counting clock to 2 kHz and uses four output compares to go to the active level in turn as the count reaches different thresholds.
Data path: SystemCoreClock → PrescalerValue and TIM_InitTimeBase → TIM_InitOc1 to TIM_InitOc4 write CCR1_Val to CCR4_Val → the count reaches each threshold → CH1 to CH4 go to the active level
1. Compute the 2 kHz counting clock and configure the time base. The system clock divided by 2000 gives the prescaler value, and the counter runs from 0 to 65535.
/* Compute the prescaler value */
PrescalerValue = (uint16_t)(SystemCoreClock / 2000) - 1;
/* Time base configuration */
TIM_InitTimBaseStruct(&TIM_TimeBaseStructure);
TIM_TimeBaseStructure.Period = 65535;
TIM_TimeBaseStructure.Prescaler = PrescalerValue;
TIM_TimeBaseStructure.ClkDiv = TIM_CLK_DIV1;
TIM_TimeBaseStructure.CounterMode = TIM_CNT_MODE_UP;
TIM_InitTimeBase(TIMx, &TIM_TimeBaseStructure);
Changing the divisor 2000 changes the counting tick, and the real times of the four thresholds scale with it.
2. Configure the CH1 output compare Active mode and disable preload. The CH1 compare value is CCR1_Val, the output polarity is high, and disabling preload makes the compare value take effect immediately.
/* Output Compare Active Mode configuration: Channel1 */
TIM_InitOcStruct(&TIM_OCInitStructure);
TIM_OCInitStructure.OCMode = TIM_OCMODE_ACTIVE;
TIM_OCInitStructure.OutputState = TIM_OUTPUT_STATE_ENABLE;
TIM_OCInitStructure.Pulse = CCR1_Val;
TIM_OCInitStructure.OCPolarity = TIM_OC_POLARITY_HIGH;
TIM_InitOc1(TIMx, &TIM_OCInitStructure);
TIM_ConfigOc1Preload(TIMx, TIM_OC_PRE_LOAD_DISABLE);
3. The other three channels reuse the same structure. CH2, CH3, and CH4 only change Pulse and disable their own preload, and the AR preload is opened last.
/* Output Compare Active Mode configuration: Channel2 */
TIM_OCInitStructure.OutputState = TIM_OUTPUT_STATE_ENABLE;
TIM_OCInitStructure.Pulse = CCR2_Val;
TIM_InitOc2(TIMx, &TIM_OCInitStructure);
TIM_ConfigOc2Preload(TIMx, TIM_OC_PRE_LOAD_DISABLE);
/* Output Compare Active Mode configuration: Channel3 */
TIM_OCInitStructure.OutputState = TIM_OUTPUT_STATE_ENABLE;
TIM_OCInitStructure.Pulse = CCR3_Val;
TIM_InitOc3(TIMx, &TIM_OCInitStructure);
TIM_ConfigOc3Preload(TIMx, TIM_OC_PRE_LOAD_DISABLE);
/* Output Compare Active Mode configuration: Channel4 */
TIM_OCInitStructure.OutputState = TIM_OUTPUT_STATE_ENABLE;
TIM_OCInitStructure.Pulse = CCR4_Val;
TIM_InitOc4(TIMx, &TIM_OCInitStructure);
TIM_ConfigOc4Preload(TIMx, TIM_OC_PRE_LOAD_DISABLE);
TIM_ConfigArPreload(TIMx, ENABLE);
The four CCRx_Val values set the ordering of the four channels, and changing any one of them changes the transition time of the matching channel.
4. Enable the counter. Output compare is produced only while the counter runs, and after enabling, the code enters an empty loop.
/* TIMx enable counter */
TIM_Enable(TIMx, ENABLE);
while (1)
{
}
Corresponding source files: src/main.c, inc/main.h
5.20.3.10 OCInactive Output compare inactive
Example directory: projects/n32g41x_EVAL/examples/TIM/OCInactive/
Enable the GPIO and GTIM2 clocks→Configure PA1 to PA4 as push-pull outputs and drive them high→Divide the GTIM2 counter clock to 2 kHz and set CH1 to CH4 to output compare inactive mode→Enable the CC1 to CC4 interrupts and start the counter→On a compare match the interrupt pulls the matching pins low
| Item | Source analysis |
|---|---|
| Function | CH1 to CH4 of GTIM2 are used for output compare; when each channel reaches its compare value the compare interrupt runs and pulls the matching PA1 to PA4 low, while the four pins are driven high during configuration. |
| Source files | src/main.c: main plus RCC_Configuration, GPIO_Configuration and NVIC_Configuration;inc/main.h: includes the GPIO, TIM and RCC headers and declares those functions;src/n32g41x_it.c and inc/n32g41x_it.h: the GTIM2_IRQHandler interrupt service routine;readme.txt: function, environment and usage notes;MDK-ARM/ and EWARM/: the Keil and IAR projects. |
| Key configuration | The counter clock is divided by SystemCoreClock / 2000, giving a 2 kHz counter clock;Period is 65535, ClkDiv is TIM_CLK_DIV1 and the counting mode is TIM_CNT_MODE_UP. All four channels use TIM_OCMODE_INACTIVE, output enabled and OCPolarity set to TIM_OC_POLARITY_HIGH, with Pulse of 1000 for CH1, 500 for CH2, 250 for CH3 and 125 for CH4;per-channel preload is disabled and TIM_ConfigArPreload is enabled. |
| Program and data path | main configures the clocks, then the NVIC and GPIO, builds the time base with TIM_InitTimBaseStruct and TIM_InitTimeBase, sets the four channels to inactive compare mode with TIM_InitOc1 to TIM_InitOc4 and enables the CC1 to CC4 interrupts, drives PA1 to PA4 high with GPIO_SetBits and starts counting with TIM_Enable;each compare match enters GTIM2_IRQHandler, which clears the per-channel flag and pulls the matching pin low with GPIO_ResetBits. |
| Main APIs | TIM_InitTimBaseStruct, TIM_InitTimeBase, TIM_InitOcStruct, TIM_InitOc1 to TIM_InitOc4, TIM_ConfigOc1Preload, TIM_ConfigArPreload, TIM_ConfigInt, TIM_Enable, TIM_GetIntStatus, TIM_ClrIntPendingBit, GPIO_InitPeripheral, GPIO_SetBits, GPIO_ResetBits |
| Verification | Build and enter debug mode, then watch PA1 to PA4 with an oscilloscope or logic analyzer: the four pins start high and are pulled low as their compare values are reached; inactive mode itself does not change the output level, so the pull-down is done by the interrupt. |
| Use note | On the eval board PA9 and PA10 are connected to the NSLINK virtual UART by jumpers by default; remove the jumpers when they are not used as a UART. Supported parts are N32G412x8L7, N32G412xBL7, N32G415x8L7 and N32G415xBL7; the development environment is KEIL MDK-ARM 5.34 or IAR EWARM 8.50.1. |
Core-code walkthrough and porting
The example sets all four GTIM2 channels to output compare inactive mode, so reaching a compare value does not change the hardware output; instead the interrupt pulls the matching pin low in software.
Data path: RCC_Configuration enables the GPIO and GTIM2 clocks → GPIO_Configuration configures PA1 to PA4 as push-pull outputs → TIM_InitTimeBase writes the 2 kHz counter clock → TIM_InitOc1 to TIM_InitOc4 set the four channels to inactive compare → GTIM2_IRQHandler pulls PA1 to PA4 low with GPIO_ResetBits in the compare interrupt
1. Clock and pin preparation. The GPIO and GTIM2 clocks are enabled first, then PA1 to PA4 are initialized as push-pull outputs so the software pull-down later has pins to drive.
/* Enable GPIO clock */
RCC_EnableAHBPeriphClk(RCC_AHB_PERIPH_GPIO, ENABLE);
/* Enable GTIM2 clock */
RCC_EnableAPB1PeriphClk(RCC_APB1_PERIPH_GTIM2, ENABLE);
/* PA1, PA2, PA3, PA4 as GPIO output */
GPIO_InitStructure.Pin = GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_3 | GPIO_PIN_4;
GPIO_InitStructure.GPIO_Mode = GPIO_MODE_OUTPUT_PP;
GPIO_InitPeripheral(GPIOA, &GPIO_InitStructure);
When moving to other pins, change this pin group and port together and point the matching GPIO_ResetBits calls in the interrupt at the same pins.
2. Compute the divider and build the time base. The counter clock is divided by SystemCoreClock / 2000 to 2 kHz and the auto-reload value is 65535, so every channel compare value is measured in that clock.
/* Compute the prescaler value */
PrescalerValue = (uint16_t)(SystemCoreClock / 2000) - 1;
/* Time base configuration */
TIM_InitTimBaseStruct(&TIM_TimeBaseStructure);
TIM_TimeBaseStructure.Period = 65535;
TIM_TimeBaseStructure.Prescaler = PrescalerValue;
TIM_TimeBaseStructure.ClkDiv = TIM_CLK_DIV1;
TIM_TimeBaseStructure.CounterMode = TIM_CNT_MODE_UP;
TIM_InitTimeBase(GTIM2, &TIM_TimeBaseStructure);
Change the divisor here to change the resolution and Period to change the maximum delay; together they set the upper bound of the four channel delays.
3. Set the channels to inactive compare mode. The four channels share one structure and only Pulse changes; for CH1 the OCMode is TIM_OCMODE_INACTIVE with preload disabled, so a compare match leaves the hardware output unchanged.
/* Output Compare Inactive Mode configuration: Channel1 */
TIM_InitOcStruct(&TIM_OCInitStructure);
TIM_OCInitStructure.OCMode = TIM_OCMODE_INACTIVE;
TIM_OCInitStructure.OutputState = TIM_OUTPUT_STATE_ENABLE;
TIM_OCInitStructure.Pulse = CCR1_Val;
TIM_OCInitStructure.OCPolarity = TIM_OC_POLARITY_HIGH;
TIM_InitOc1(GTIM2, &TIM_OCInitStructure);
TIM_ConfigOc1Preload(GTIM2, TIM_OC_PRE_LOAD_DISABLE);
Change the delay of one channel through its CCRx_Val; in inactive mode the pin level is not changed by hardware, so the actual pull-down is done by the interrupt.
4. Drive high first, then pull low in the interrupt. Before starting, PA1 to PA4 are driven high and the four compare interrupts are enabled; after counting starts each match enters GTIM2_IRQHandler, which clears the flag and pulls the matching pin low.
/* TIM IT enable */
TIM_ConfigInt(GTIM2, TIM_INT_CC1 | TIM_INT_CC2 | TIM_INT_CC3 | TIM_INT_CC4, ENABLE);
/* Set output pins */
GPIO_SetBits(GPIOA, GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_3 | GPIO_PIN_4);
/* GTIM2 enable counter */
TIM_Enable(GTIM2, ENABLE);
if (TIM_GetIntStatus(GTIM2, TIM_INT_CC1) != RESET)
{
/* Clear GTIM2 Capture Compare1 interrupt pending bit */
TIM_ClrIntPendingBit(GTIM2, TIM_INT_CC1);
GPIO_ResetBits(GPIOA, GPIO_PIN_1);
}
When porting, check the interrupt vector GTIM2_IRQn and the name GTIM2_IRQHandler together, and change both when another timer is used.
Corresponding source files: src/main.c, src/n32g41x_it.c
5.20.3.11 OCToggle Output compare toggle
Example directory: projects/n32g41x_EVAL/examples/TIM/OCToggle/
Enable the GPIO and GTIM1 clocks→Configure PA0 to PA3 as CH1 to CH4 alternate-function outputs→Build an 8 MHz counter time base and set the four channels to output compare toggle mode→Clear the compare and update flags, enable the CC1 to CC4 interrupts and start the counter→The pin toggles on a compare match and the interrupt accumulates the next compare value
| Item | Source analysis |
|---|---|
| Function | CH1 to CH4 of GTIM1 run in output compare toggle mode, so the matching pin toggles when a compare value is reached, and the interrupt adds a fixed amount to the compare value, producing a 50 percent duty cycle square wave. |
| Source files | src/main.c: main plus RCC_Configuration, GPIO_Configuration and NVIC_Configuration;inc/main.h: the TIMx, per-channel pin and alternate-function macros, interrupt mapping and function declarations;src/n32g41x_it.c and inc/n32g41x_it.h: the TIMx_IRQHandler interrupt service routine and the compare value accumulation;readme.txt: function, environment and usage notes;MDK-ARM/ and EWARM/: the Keil and IAR projects. |
| Key configuration | TIMx is GTIM1 with clock RCC_APB1_PERIPH_GTIM1;CH1 is PA0, CH2 is PA1, CH3 is PA2 and CH4 is PA3, all GPIO_MODE_AF_PP with GPIO_AF2. The counter clock is divided by SystemCoreClock / 8000000 to 8 MHz and Period is 0xFFFFFFFF;all four channels use TIM_OCMODE_TOGGLE, output enabled and OCPolarity set to TIM_OC_POLARITY_LOW, with Pulse of 32768, 16384, 8192 and 4096, and preload disabled. |
| Program and data path | main configures the clocks, GPIO and NVIC, builds the 8 MHz time base with TIM_InitTimeBase and sets the four channels to toggle mode with TIM_InitOc1 to TIM_InitOc4;it then clears the compare and update flags with TIM_ClrIntPendingBit, enables the CC1 to CC4 interrupts with TIM_ConfigInt and starts with TIM_Enable;each compare match enters TIMx_IRQHandler, which reads the current compare value with TIM_GetCapx and writes back its sum with CCRx_Val using TIM_SetCmpx. |
| Main APIs | TIM_InitTimBaseStruct, TIM_InitTimeBase, TIM_InitOcStruct, TIM_InitOc1 to TIM_InitOc4, TIM_ConfigOc1Preload, TIM_ConfigOc4Preload, TIM_ClrIntPendingBit, TIM_ConfigInt, TIM_Enable, TIM_GetIntStatus, TIM_GetCap1, TIM_SetCmp1, GPIO_InitPeripheral |
| Verification | Build and enter debug mode, then watch PA0 to PA3 with an oscilloscope or logic analyzer: the period of each output is set by CCRx_Val with the 8 MHz counter clock, and the duty cycle is fixed at 50 percent. |
| Use note | On the eval board PA9 and PA10 are connected to the NSLINK virtual UART by jumpers by default; remove the jumpers when they are not used as a UART. Supported parts are N32G412x8L7, N32G412xBL7, N32G415x8L7 and N32G415xBL7; the development environment is KEIL MDK-ARM 5.34 or IAR EWARM 8.50.1. |
Core-code walkthrough and porting
The example points TIMx at GTIM1, runs the four channels in output compare toggle mode and lets the interrupt push the next compare value forward by a fixed amount.
Data path: RCC_Configuration enables the GPIO and GTIM1 clocks → GPIO_Configuration configures PA0 to PA3 as CH1 to CH4 alternate-function outputs → TIM_InitTimeBase builds the 8 MHz time base → TIM_InitOc1 to TIM_InitOc4 select toggle mode → TIMx_IRQHandler accumulates the compare value and triggers the next toggle
1. Gather the timer and four channel parameters in macros. inc/main.h defines TIMx as GTIM1 and gives the pin, port and alternate number of each channel, so all later configuration goes through this macro set.
#define TIMx GTIM1
#define TIMx_CLK RCC_APB1_PERIPH_GTIM1
/* GTIM1 CH1: PA0 */
#define TIMx_CH1_PIN GPIO_PIN_0
#define TIMx_CH1_GPIO GPIOA
#define TIMx_CH1_AF GPIO_AF2
When porting to another timer, change TIMx, TIMx_CLK, the four channel pin and alternate macros, and the TIMx_IRQn and TIMx_IRQHandler mapping together.
2. Build the 8 MHz counter time base. The counter clock is divided by SystemCoreClock / 8000000 and the auto-reload value is set to full scale so the compare values are not limited by the period.
/* Compute the prescaler value */
PrescalerValue = (uint16_t)(SystemCoreClock / 8000000) - 1;
/* Time base configuration */
TIM_InitTimBaseStruct(&TIM_TimeBaseStructure);
TIM_TimeBaseStructure.Period = 0xFFFFFFFF;
TIM_TimeBaseStructure.Prescaler = PrescalerValue;
TIM_TimeBaseStructure.ClkDiv = TIM_CLK_DIV1;
TIM_TimeBaseStructure.CounterMode = TIM_CNT_MODE_UP;
TIM_InitTimeBase(TIMx, &TIM_TimeBaseStructure);
The compare values are measured in 8 MHz; change the divisor here or the CCRx_Val of each channel to change the toggle rate.
3. Set the channels to toggle mode. The four channels share the structure and OCMode is TIM_OCMODE_TOGGLE; for CH1 the initial value and polarity are written before enabling, with preload disabled.
/* Output Compare Toggle Mode configuration: Channel1 */
TIM_InitOcStruct(&TIM_OCInitStructure);
TIM_OCInitStructure.OCMode = TIM_OCMODE_TOGGLE;
TIM_OCInitStructure.OutputState = TIM_OUTPUT_STATE_ENABLE;
TIM_OCInitStructure.Pulse = CCR1_Val;
TIM_OCInitStructure.OCPolarity = TIM_OC_POLARITY_LOW;
TIM_InitOc1(TIMx, &TIM_OCInitStructure);
TIM_ConfigOc1Preload(TIMx, TIM_OC_PRE_LOAD_DISABLE);
With preload disabled a compare value written in the interrupt takes effect at once; with preload enabled the next compare value would only be loaded on an update event.
4. Clear the flags, enable interrupts and start. The update flag and the four compare flags are cleared before the interrupts are enabled, then CC1 to CC4 are enabled and counting starts.
TIM_ClrIntPendingBit(TIMx, TIM_INT_UPDATE);
TIM_ClrIntPendingBit(TIMx, TIM_INT_CC1);
TIM_ClrIntPendingBit(TIMx, TIM_INT_CC2);
TIM_ClrIntPendingBit(TIMx, TIM_INT_CC3);
TIM_ClrIntPendingBit(TIMx, TIM_INT_CC4);
/* TIM IT enable */
TIM_ConfigInt(TIMx, TIM_INT_CC1 | TIM_INT_CC2 | TIM_INT_CC3 | TIM_INT_CC4, ENABLE);
/* TIM enable counter */
TIM_Enable(TIMx, ENABLE);
5. Accumulate the next compare value in the interrupt. On every compare match the flag is cleared, the current compare value is read back and its sum with CCRx_Val is written, giving evenly spaced toggles.
/* TIMx_CH1 toggling */
if (TIM_GetIntStatus(TIMx, TIM_INT_CC1) != RESET)
{
TIM_ClrIntPendingBit(TIMx, TIM_INT_CC1);
capture = TIM_GetCap1(TIMx);
TIM_SetCmp1(TIMx, capture + CCR1_Val);
}
Change the output frequency through the matching CCRx_Val; capture is a file-scope variable shared by the four branches.
Corresponding source files: src/main.c, inc/main.h, src/n32g41x_it.c
5.20.3.12 OnePulse One-pulse output
Example directory: projects/n32g41x_EVAL/examples/TIM/OnePulse/
Enable the GPIO and GTIM1 clocks→Configure PA0 as CH1 output, PA1 as CH2 input and PA3 as a plain output→Build the time base, set CH1 to PWM2 output and CH2 to rising-edge capture→Select one-pulse mode and the TI2FP2 trigger, and set the slave mode to trigger mode→The main loop sends a rising edge on PA3 when a software trigger is requested
| Item | Source analysis |
|---|---|
| Function | CH2 of GTIM1 is set up as a rising-edge input capture and used as the trigger source; in one-pulse mode a detected rising edge makes CH1 output a single pulse whose width is set by Period - Pulse. The main loop sends a trigger edge on PA3 when gSendTrigEn is set. |
| Source files | src/main.c: main, RCC_Configuration, GPIO_Configuration and SendOneTrig;inc/main.h: the TIMx, CH1 and CH2 pin and alternate macros plus the SendOneTrig declaration;src/n32g41x_it.c and inc/n32g41x_it.h: the interrupt service routines;readme.txt: function, environment and usage notes;MDK-ARM/ and EWARM/: the Keil and IAR projects. |
| Key configuration | TIMx is GTIM1;CH1 is PA0 and CH2 is PA1, both GPIO_MODE_AF_PP with GPIO_AF2, and PA3 is GPIO_MODE_OUTPUT_PP. The counter clock is divided by SystemCoreClock / 8000000 to 8 MHz and Period is 65535;CH1 uses TIM_OCMODE_PWM2 with Pulse 16383 and TIM_OC_POLARITY_HIGH;CH2 uses capture polarity TIM_IC_POLARITY_RISING, selection TIM_IC_SELECTION_DIRECTTI, prescaler TIM_IC_PSC_DIV1 and filter 0. |
| Program and data path | main configures the clocks and GPIO, builds the time base, sets CH1 to PWM2 output, configures CH2 for rising-edge direct capture with TIM_ICInit, then selects single mode with TIM_SelectOnePulseMode, the TI2FP2 trigger with TIM_SelectInputTrig and trigger mode with TIM_SelectSlaveMode;the main loop calls SendOneTrig repeatedly, which clears gSendTrigEn when it is true and drives PA3 high then low to form a trigger pulse. |
| Main APIs | TIM_InitTimBaseStruct, TIM_InitTimeBase, TIM_InitOcStruct, TIM_InitOc1, TIM_InitIcStruct, TIM_ICInit, TIM_SelectOnePulseMode, TIM_SelectInputTrig, TIM_SelectSlaveMode, GPIO_InitStruct, GPIO_InitPeripheral, GPIO_SetBits, GPIO_ResetBits |
| Verification | Connect PA3 to PA1 and watch CH1 (PA0) with an oscilloscope or logic analyzer: after setting gSendTrigEn to 1 in the debug window the program sends a rising edge on PA3 and CH1 outputs a single pulse;changing Pulse changes the pulse width. |
| Use note | PA3 and PA1 must be wired together for self-triggering; on the eval board PA9 and PA10 are connected to the NSLINK virtual UART by jumpers by default, so remove the jumpers when they are not used as a UART. Supported parts are N32G412x8L7, N32G412xBL7, N32G415x8L7 and N32G415xBL7; the development environment is KEIL MDK-ARM 5.34 or IAR EWARM 8.50.1. |
Core-code walkthrough and porting
The example generates a trigger edge on PA3 in software, feeds it into one-pulse mode through PA1 (CH2), and outputs a width-controlled pulse on PA0 (CH1).
Data path: SendOneTrig toggles PA3 → the rising edge on PA1 is captured by CH2 → the TI2FP2 trigger selected by TIM_SelectInputTrig starts the counter → CH1 outputs a single pulse in PWM2 mode → the pulse width is observed on PA0 with an oscilloscope
1. Configure the three pins from the outside in. CH1 and CH2 are set to alternate-function push-pull with their own alternate numbers, and PA3 is configured separately as a plain push-pull output that acts as the software trigger source.
/* GTIM1 CH1: PA0 */
GPIO_InitStructure.Pin = TIMx_CH1_PIN;
GPIO_InitStructure.GPIO_Mode = GPIO_MODE_AF_PP;
GPIO_InitStructure.GPIO_Alternate = TIMx_CH1_AF;
GPIO_InitPeripheral(TIMx_CH1_GPIO, &GPIO_InitStructure);
/* GTIM1 CH2: PA1 */
GPIO_InitStructure.Pin = TIMx_CH2_PIN;
GPIO_InitStructure.GPIO_Alternate = TIMx_CH2_AF;
GPIO_InitPeripheral(TIMx_CH2_GPIO, &GPIO_InitStructure);
/* PA3: GPIO output for trigger */
GPIO_InitStructure.Pin = GPIO_PIN_3;
GPIO_InitStructure.GPIO_Mode = GPIO_MODE_OUTPUT_PP;
GPIO_InitPeripheral(GPIOA, &GPIO_InitStructure);
When porting, the pins and alternate numbers come from the CH1, CH2 and PA3 macros in inc/main.h, so check them together when changing boards.
2. Build the 8 MHz time base. The counter clock is divided by SystemCoreClock / 8000000 and the auto-reload value is 65535, so the pulse width is set by the difference between Period and Pulse.
/* Compute the prescaler value */
PrescalerValue = (uint16_t)(SystemCoreClock / 8000000) - 1;
/* Time base configuration */
TIM_InitTimBaseStruct(&TIM_TimeBaseStructure);
TIM_TimeBaseStructure.Period = 65535;
TIM_TimeBaseStructure.Prescaler = PrescalerValue;
TIM_TimeBaseStructure.ClkDiv = TIM_CLK_DIV1;
TIM_TimeBaseStructure.CounterMode = TIM_CNT_MODE_UP;
TIM_InitTimeBase(TIMx, &TIM_TimeBaseStructure);
To change the pulse delay and width, change Pulse and Period respectively, both counted at 8 MHz.
3. Use PWM2 mode for the CH1 output. The output channel uses TIM_OCMODE_PWM2 with Pulse 16383 and high polarity, which in one-pulse mode sets the pulse delay and width.
/* TIMx PWM2 Mode configuration: Channel1 */
TIM_InitOcStruct(&TIM_OCInitStructure);
TIM_OCInitStructure.OCMode = TIM_OCMODE_PWM2;
TIM_OCInitStructure.OutputState = TIM_OUTPUT_STATE_ENABLE;
TIM_OCInitStructure.Pulse = 16383;
TIM_OCInitStructure.OCPolarity = TIM_OC_POLARITY_HIGH;
TIM_InitOc1(TIMx, &TIM_OCInitStructure);
4. Capture the CH2 rising edge and select it as the trigger source. The input structure sets CH2 to rising-edge direct capture, then TI2FP2 is selected as the trigger input, the slave mode is set to trigger mode and single one-pulse mode is enabled.
/* TIMx configuration in Input Capture Mode */
TIM_InitIcStruct(&TIM_ICInitStructure);
TIM_ICInitStructure.Channel = TIM_CH_2;
TIM_ICInitStructure.ICPolarity = TIM_IC_POLARITY_RISING;
TIM_ICInitStructure.ICSelection = TIM_IC_SELECTION_DIRECTTI;
TIM_ICInitStructure.ICPrescaler = TIM_IC_PSC_DIV1;
TIM_ICInitStructure.ICFilter = 0;
TIM_ICInit(TIMx, &TIM_ICInitStructure);
/* One Pulse Mode selection */
TIM_SelectOnePulseMode(TIMx, TIM_OPMODE_SINGLE);
/* Input Trigger selection */
TIM_SelectInputTrig(TIMx, TIM_TRIG_SEL_TI2FP2);
/* Slave Mode selection: Trigger Mode */
TIM_SelectSlaveMode(TIMx, TIM_SLAVE_MODE_TRIG);
When the trigger source is changed, update both the TIM_SelectInputTrig selection and the matching capture channel so that both point at the same TIxFP.
5. Send the software trigger edge on PA3. When the enable flag is set, SendOneTrig clears it, drives PA3 high, holds it briefly and drives it low again, forming a rising edge that CH2 can capture.
if (gSendTrigEn)
{
gSendTrigEn = 0;
GPIO_SetBits(GPIOA, GPIO_PIN_3);
{
uint32_t i = 0;
while (i++ < 10)
;
}
GPIO_ResetBits(GPIOA, GPIO_PIN_3);
}
The trigger pulse width is set by this delay loop; when it is changed it must stay wide enough for the CH2 capture filter and edge detection.
Corresponding source files: src/main.c, inc/main.h
5.20.3.13 Parallel_Synchro Parallel gated synchronization
Example directory: projects/n32g41x_EVAL/examples/TIM/Parallel_Synchro/
Enable the GPIO and GTIM1, GTIM2 and GTIM3 clocks→Configure PA0, PB4 and PA6 as the CH1 alternate-function outputs of the three timers→Build the GTIM1, GTIM2 and GTIM3 time bases and configure master and slave PWM1 outputs→Set GTIM1 as the master timer and select its update event as the trigger output→Set GTIM2 and GTIM3 to gated slave mode and select their trigger inputs
| Item | Source analysis |
|---|---|
| Function | GTIM1 acts as the master timer and uses its update event as the trigger output to control the start and stop of GTIM2 and GTIM3 through gated mode, so the two slave outputs produce PWM waveforms whose periods are integer multiples of the master period. |
| Source files | src/main.c: main, RCC_Configuration and GPIO_Configuration;inc/main.h: the TIMx, TIMy and TIMz timers with their clocks and CH1 pin and alternate macros;readme.txt: function, environment and usage notes;MDK-ARM/ and EWARM/: the Keil and IAR projects. |
| Key configuration | The master TIMx is GTIM1 with CH1 on PA0 and GPIO_AF2;the slave TIMy is GTIM2 with CH1 on PB4 and GPIO_AF8;the slave TIMz is GTIM3 with CH1 on PA6 and GPIO_AF12. All three use Prescaler 0, ClkDiv TIM_CLK_DIV1 and up counting;Period is 255 for the master, 9 and 4 for the slaves.The master channel uses Pulse 64 and the slave channels Pulse 3, all in TIM_OCMODE_PWM1 with TIM_OC_POLARITY_HIGH. |
| Program and data path | main configures the clocks and GPIO, then builds the GTIM1, GTIM2 and GTIM3 time bases with TIM_InitTimeBase;TIM_InitOc1 sets the master channel to PWM1, TIM_SelectMasterSlaveMode enables master and slave mode and TIM_SelectOutputTrig selects the update event as the trigger output;for TIMy and TIMz it sets PWM1 with TIM_InitOc1 and selects gated mode and their trigger inputs with TIM_SelectSlaveMode and TIM_SelectInputTrig, then enables the PWM output and starts the three counters. |
| Main APIs | TIM_InitTimBaseStruct, TIM_InitTimeBase, TIM_InitOcStruct, TIM_InitOc1, TIM_SelectMasterSlaveMode, TIM_SelectOutputTrig, TIM_SelectSlaveMode, TIM_SelectInputTrig, TIM_EnableCtrlPwmOutputs, TIM_Enable, GPIO_InitStruct, GPIO_InitPeripheral |
| Verification | Watch GTIM1 CH1 (PA0), GTIM2 CH1 (PB4) and GTIM3 CH1 (PA6) at the same time with an oscilloscope or logic analyzer: the GTIM2 period is 10 times the master period and the GTIM3 period is 5 times the master period. |
| Use note | On the eval board PA9 and PA10 are connected to the NSLINK virtual UART by jumpers by default; remove the jumpers when they are not used as a UART. Supported parts are N32G412x8L7, N32G412xBL7, N32G415x8L7 and N32G415xBL7; the development environment is KEIL MDK-ARM 5.34 or IAR EWARM 8.50.1. |
Core-code walkthrough and porting
The example makes GTIM1 the master timer and GTIM2 and GTIM3 gated slaves, so the master update event controls the start and stop of the two slave counters.
Data path: TIM_InitTimeBase builds the three time bases → TIM_InitOc1 configures the master and slave PWM outputs → TIM_SelectOutputTrig sends the master update event to the trigger output → TIM_SelectSlaveMode and TIM_SelectInputTrig make the two slaves follow in gated mode → the three PWM waveforms are output on PA0, PB4 and PA6
1. Declare the master and slave timers in macros. inc/main.h gives the timer name, clock and CH1 pin and alternate macros of the master and the two slaves in turn, fixing the master and slave relationship in macros.
/* Master: GTIM1(TIM2), CH1=PA0(AF2) */
#define TIMx GTIM1
#define TIMx_CLK RCC_APB1_PERIPH_GTIM1
#define TIMx_CH1_PIN GPIO_PIN_0
#define TIMx_CH1_GPIO GPIOA
#define TIMx_CH1_AF GPIO_AF2
/* Slave1: GTIM2(TIM3), CH1=PB4(AF8), ITR1=GTIM1 */
#define TIMy GTIM2
#define TIMy_CLK RCC_APB1_PERIPH_GTIM2
#define TIMy_CH1_PIN GPIO_PIN_4
#define TIMy_CH1_GPIO GPIOB
#define TIMy_CH1_AF GPIO_AF8
/* Slave2: GTIM3(TIM4), CH1=PA6(AF12), ITR1=GTIM1 */
#define TIMz GTIM3
#define TIMz_CLK RCC_APB1_PERIPH_GTIM3
#define TIMz_CH1_PIN GPIO_PIN_6
#define TIMz_CH1_GPIO GPIOA
#define TIMz_CH1_AF GPIO_AF12
When porting to another timer combination, change the three timer names, clocks and CH1 pin and alternate macros together, and check the matching pins and ports in GPIO_Configuration.
2. Time base of the master and two slaves. The three timers share one structure and only Period changes; the master Period is 255 and the two slaves use 9 and 4.
/* Time base configuration */
TIM_InitTimBaseStruct(&TIM_TimeBaseStructure);
TIM_TimeBaseStructure.Period = 255;
TIM_TimeBaseStructure.Prescaler = 0;
TIM_TimeBaseStructure.ClkDiv = TIM_CLK_DIV1;
TIM_TimeBaseStructure.CounterMode = TIM_CNT_MODE_UP;
TIM_InitTimeBase(TIMx, &TIM_TimeBaseStructure);
TIM_TimeBaseStructure.Period = 9;
TIM_InitTimeBase(TIMy, &TIM_TimeBaseStructure);
TIM_TimeBaseStructure.Period = 4;
TIM_InitTimeBase(TIMz, &TIM_TimeBaseStructure);
To change the period ratio, change the three Period values; the slave ratio is set by the integer multiple relationship with the master period.
3. Master output and trigger source. The master channel runs in PWM1 mode with Pulse 64; TIM_SelectMasterSlaveMode enables master and slave mode and TIM_SelectOutputTrig selects the update event as the trigger output.
/* Master Configuration in PWM1 Mode */
TIM_InitOcStruct(&TIM_OCInitStructure);
TIM_OCInitStructure.OCMode = TIM_OCMODE_PWM1;
TIM_OCInitStructure.OutputState = TIM_OUTPUT_STATE_ENABLE;
TIM_OCInitStructure.Pulse = 64;
TIM_OCInitStructure.OCPolarity = TIM_OC_POLARITY_HIGH;
TIM_InitOc1(TIMx, &TIM_OCInitStructure);
/* Select the Master Slave Mode */
TIM_SelectMasterSlaveMode(TIMx, TIM_MASTER_SLAVE_MODE_ENABLE);
/* Master Mode selection */
TIM_SelectOutputTrig(TIMx, TIM_TRGO_SRC_UPDATE);
The trigger output uses the update event; when another source such as a compare event is used, check the slave trigger input selection at the same time.
4. The two slaves follow in gated mode. The slave channels are also PWM1 with Pulse 3; TIM_SelectSlaveMode selects gated mode and TIM_SelectInputTrig uses TIM_TRIG_SEL_IN_TR2 and TIM_TRIG_SEL_IN_TR1 respectively, so the slave counting is controlled by the master trigger signal.
/* Slaves Configuration: PWM1 Mode */
TIM_OCInitStructure.OCMode = TIM_OCMODE_PWM1;
TIM_OCInitStructure.OutputState = TIM_OUTPUT_STATE_ENABLE;
TIM_OCInitStructure.Pulse = 3;
TIM_InitOc1(TIMy, &TIM_OCInitStructure);
TIM_InitOc1(TIMz, &TIM_OCInitStructure);
/* Slave Mode selection: TIMy, ITR2 = TIMx */
TIM_SelectSlaveMode(TIMy, TIM_SLAVE_MODE_GATED);
TIM_SelectInputTrig(TIMy, TIM_TRIG_SEL_IN_TR2);
/* Slave Mode selection: TIMz, ITR1 = TIMx */
TIM_SelectSlaveMode(TIMz, TIM_SLAVE_MODE_GATED);
TIM_SelectInputTrig(TIMz, TIM_TRIG_SEL_IN_TR1);
TIM_EnableCtrlPwmOutputs(TIMz, ENABLE);
/* TIM enable counter */
TIM_Enable(TIMy, ENABLE);
TIM_Enable(TIMz, ENABLE);
TIM_Enable(TIMx, ENABLE);
The source comment says both slaves take their trigger input from ITR1 (GTIM1), while the code uses TIM_TRIG_SEL_IN_TR2 for GTIM2 and TIM_TRIG_SEL_IN_TR1 for GTIM3, and TIM_EnableCtrlPwmOutputs is called only for TIMz. When porting to another chip, check the ITRx mapping and the PWM output enable range item by item instead of following the comment alone.
Corresponding source files: src/main.c, inc/main.h
5.20.3.14 PWM_Input PWM input capture
Example directory: projects/n32g41x_EVAL/examples/TIM/PWM_Input/
Enable the GPIO and GTIM1 clocks→Configure PA1 as CH2 alternate-function input and PA3 as a plain output→Set CH2 to PWM input mode, select the TI2FP2 trigger and set reset slave mode→Enable the CC2 interrupt and start the counter→The main loop generates a square wave on PA3 and the capture on PA1 computes the duty cycle and frequency
| Item | Source analysis |
|---|---|
| Function | CH2 of GTIM1 is configured in PWM input mode, so the same input signal is captured on two paths to give the period and the high time; the main loop outputs a square wave on PA3 that is wired to PA1, and the interrupt computes the duty cycle and frequency variables from the capture values. |
| Source files | src/main.c: main, RCC_Configuration, GPIO_Configuration and NVIC_Configuration;inc/main.h: the TIMx, CH2 pin and alternate macros, interrupt mapping and function declarations;src/n32g41x_it.c and inc/n32g41x_it.h: the TIMx_IRQHandler interrupt service routine and the Frequency and DutyCycle computation;readme.txt: function, environment and usage notes;MDK-ARM/ and EWARM/: the Keil and IAR projects. |
| Key configuration | TIMx is GTIM1.CH2 is PA1 with GPIO_MODE_AF_PP and GPIO_AF2, and PA3 is GPIO_MODE_OUTPUT_PP. The capture structure uses Channel = TIM_CH_2, ICPolarity = TIM_IC_POLARITY_RISING, ICSelection = TIM_IC_SELECTION_DIRECTTI, ICPrescaler = TIM_IC_PSC_DIV1 and ICFilter = 0x0;the slave mode is TIM_SLAVE_MODE_RESET, the trigger input is TIM_TRIG_SEL_TI2FP2 and master and slave mode is enabled. |
| Program and data path | main configures the clocks, GPIO and NVIC, then TIM_ConfigPwmIc sets CH2 to PWM input, TIM_SelectInputTrig selects TI2FP2, TIM_SelectSlaveMode selects reset mode and TIM_SelectMasterSlaveMode enables master and slave mode, after which TIM_Enable starts and TIM_ConfigInt opens the CC2 interrupt;the main loop produces a square wave on PA3; each CC2 trigger enters TIMx_IRQHandler, which takes the period from TIM_GetCap2 and the high time from TIM_GetCap1 to compute DutyCycle and Frequency. |
| Main APIs | TIM_InitIcStruct, TIM_ConfigPwmIc, TIM_SelectInputTrig, TIM_SelectSlaveMode, TIM_SelectMasterSlaveMode, TIM_Enable, TIM_ConfigInt, TIM_ClrIntPendingBit, TIM_GetCap1, TIM_GetCap2, GPIO_InitStruct, GPIO_InitPeripheral, GPIO_SetBits, GPIO_ResetBits |
| Verification | Connect PA3 to PA1 and add Frequency and DutyCycle to the watch window;while running the two variables update with the square wave sent from PA3, giving the captured frequency and duty cycle. |
| Use note | PA3 and PA1 must be wired together; on the eval board PA9 and PA10 are connected to the NSLINK virtual UART by jumpers by default, so remove the jumpers when they are not used as a UART. Supported parts are N32G412x8L7, N32G412xBL7, N32G415x8L7 and N32G415xBL7; the development environment is KEIL MDK-ARM 5.34 or IAR EWARM 8.50.1. |
Core-code walkthrough and porting
The example feeds the square wave on PA3 back into CH2 and uses PWM input mode to measure the period and duty cycle at once, with the results placed in two global variables.
Data path: the main loop produces a square wave on PA3 → the TI2FP2 rising edge on CH2 triggers the capture and resets the counter → TIMx_IRQHandler reads the period from TIM_GetCap2 and the high time from TIM_GetCap1 → DutyCycle and Frequency are computed
1. Wire CH2 as alternate-function input and PA3 as the signal source. CH2 is set to alternate-function push-pull with its alternate number, and PA3 is set separately as a plain push-pull output that generates the square wave under test.
/* TIMx CH2 */
GPIO_InitStructure.Pin = TIMx_CH2_PIN;
GPIO_InitStructure.GPIO_Mode = GPIO_MODE_AF_PP;
GPIO_InitStructure.GPIO_Alternate = TIMx_CH2_AF;
GPIO_InitPeripheral(TIMx_CH2_GPIO, &GPIO_InitStructure);
/* PA3: GPIO output for generating PWM signal */
GPIO_InitStructure.Pin = GPIO_PIN_3;
GPIO_InitStructure.GPIO_Mode = GPIO_MODE_OUTPUT_PP;
GPIO_InitPeripheral(GPIOA, &GPIO_InitStructure);
When porting, the pins and alternate numbers come from the CH2 macros in inc/main.h and the PA3 pin definition, so check them together when changing boards.
2. Set up PWM input and reset slave mode in one go. TIM_ConfigPwmIc maps the input onto both IC1 and IC2, then TI2FP2 is selected as the trigger input, reset slave mode is set, master and slave mode is enabled and finally counting and the CC2 interrupt are started.
TIM_InitIcStruct(&TIM_ICInitStructure);
TIM_ICInitStructure.Channel = TIM_CH_2;
TIM_ICInitStructure.ICPolarity = TIM_IC_POLARITY_RISING;
TIM_ICInitStructure.ICSelection = TIM_IC_SELECTION_DIRECTTI;
TIM_ICInitStructure.ICPrescaler = TIM_IC_PSC_DIV1;
TIM_ICInitStructure.ICFilter = 0x0;
TIM_ConfigPwmIc(TIMx, &TIM_ICInitStructure);
/* Select the TIMx Input Trigger: TI2FP2 */
TIM_SelectInputTrig(TIMx, TIM_TRIG_SEL_TI2FP2);
/* Select the slave Mode: Reset Mode */
TIM_SelectSlaveMode(TIMx, TIM_SLAVE_MODE_RESET);
/* Enable the Master/Slave Mode */
TIM_SelectMasterSlaveMode(TIMx, TIM_MASTER_SLAVE_MODE_ENABLE);
/* TIM enable counter */
TIM_Enable(TIMx, ENABLE);
/* Enable the CC2 Interrupt Request */
TIM_ConfigInt(TIMx, TIM_INT_CC2, ENABLE);
PWM input mode supports only the CH1 and CH2 channels, so when changing channels update the Channel, the trigger selection and the reset slave mode combination together.
3. The main loop generates the square wave under test. The main loop drives PA3 high, delays, drives it low and delays again, forming a square wave with about 50 percent duty cycle into CH2.
while (1)
{
GPIO_SetBits(GPIOA, GPIO_PIN_3);
{
volatile uint32_t i = 0;
while (i++ < 10)
;
}
GPIO_ResetBits(GPIOA, GPIO_PIN_3);
{
volatile uint32_t i = 0;
while (i++ < 10)
;
}
}
Changing the two delays changes the duty cycle and frequency of the input square wave, which shows whether the capture result follows.
4. Compute the duty cycle and frequency in the interrupt. On each CC2 trigger the flag is cleared first, then TIM_GetCap2 reads the period and TIM_GetCap1 reads the high time; dividing them gives the duty cycle and dividing the system clock by the period gives the frequency.
/* Clear TIMx Capture compare interrupt pending bit */
TIM_ClrIntPendingBit(TIMx, TIM_INT_CC2);
/* Get the Input Capture value */
IC2Value = TIM_GetCap2(TIMx);
if (IC2Value != 0)
{
/* Duty cycle computation */
DutyCycle = (TIM_GetCap1(TIMx) * 100) / IC2Value;
/* Frequency computation */
Frequency = SystemCoreClock / IC2Value;
}
else
{
DutyCycle = 0;
Frequency = 0;
}
The period is checked for zero before dividing, which avoids a divide by zero when the input signal stops; keep this guard when porting.
Corresponding source files: src/main.c, src/n32g41x_it.c
5.20.3.15 PWM_Output PWM output
Example directory: projects/n32g41x_EVAL/examples/TIM/PWM_Output/
Enable the GPIO and GTIM1 clocks→Configure PA0 to PA3 as CH1 to CH4 alternate-function outputs→Build a 16 MHz time base and set the four channels to PWM1 mode→Enable the per-channel and auto-reload preload and start the counter
| Item | Source analysis |
|---|---|
| Function | CH1 to CH4 of GTIM1 output four PWM waveforms with the same period and different duty cycles, where each duty cycle is set by the ratio of its compare value to the auto-reload value. |
| Source files | src/main.c: main, RCC_Configuration and GPIO_Configuration;inc/main.h: the TIMx timer and the pin and alternate macros of the four channels;readme.txt: function, environment and usage notes;MDK-ARM/ and EWARM/: the Keil and IAR projects. |
| Key configuration | TIMx is GTIM1.CH1 is PA0, CH2 is PA1, CH3 is PA2 and CH4 is PA3, all GPIO_MODE_AF_PP with GPIO_AF2. The counter clock is divided by SystemCoreClock / 16000000 to 16 MHz and Period is 1200;the four channels use TIM_OCMODE_PWM1, output enabled and TIM_OC_POLARITY_HIGH, with Pulse of 600, 300, 150 and 75;both the per-channel preload and the auto-reload preload are enabled. |
| Program and data path | main configures the clocks and GPIO, builds the 16 MHz time base, sets the four channels to PWM1 with TIM_InitOc1 to TIM_InitOc4 and enables their preload;it then enables the auto-reload preload with TIM_ConfigArPreload and starts counting with TIM_Enable, so the four outputs continuously produce PWM with different duty cycles. |
| Main APIs | TIM_InitTimBaseStruct, TIM_InitTimeBase, TIM_InitOcStruct, TIM_InitOc1, TIM_InitOc2, TIM_InitOc3, TIM_InitOc4, TIM_ConfigOc1Preload, TIM_ConfigOc4Preload, TIM_ConfigArPreload, TIM_Enable, GPIO_InitStruct, GPIO_InitPeripheral |
| Verification | Watch PA0 to PA3 with an oscilloscope or logic analyzer: the four outputs have the same period and duty cycles of about 50, 25, 12.5 and 6.25 percent. |
| Use note | On the eval board PA9 and PA10 are connected to the NSLINK virtual UART by jumpers by default; remove the jumpers when they are not used as a UART. Supported parts are N32G412x8L7, N32G412xBL7, N32G415x8L7 and N32G415xBL7; the development environment is KEIL MDK-ARM 5.34 or IAR EWARM 8.50.1. |
Core-code walkthrough and porting
The example configures four PWM channels with one structure and only changes the compare value, giving four waveforms with the same period and decreasing duty cycles.
Data path: TIM_InitTimeBase writes 16 MHz and Period 1200 → TIM_InitOc1 to TIM_InitOc4 select PWM1 and write their Pulse → the per-channel and auto-reload preload are enabled → TIM_Enable starts → four PWM waveforms are output on PA0 to PA3
1. Configure the four pins as alternate-function outputs first. The first channel writes the mode and alternate number in full, and the other three only change the pin and alternate number while reusing the same push-pull alternate-function configuration.
/* TIMx CH1 */
GPIO_InitStructure.Pin = TIMx_CH1_PIN;
GPIO_InitStructure.GPIO_Mode = GPIO_MODE_AF_PP;
GPIO_InitStructure.GPIO_Alternate = TIMx_CH1_AF;
GPIO_InitPeripheral(TIMx_CH1_GPIO, &GPIO_InitStructure);
/* TIMx CH2 */
GPIO_InitStructure.Pin = TIMx_CH2_PIN;
GPIO_InitStructure.GPIO_Alternate = TIMx_CH2_AF;
GPIO_InitPeripheral(TIMx_CH2_GPIO, &GPIO_InitStructure);
/* TIMx CH3 */
GPIO_InitStructure.Pin = TIMx_CH3_PIN;
GPIO_InitStructure.GPIO_Alternate = TIMx_CH3_AF;
GPIO_InitPeripheral(TIMx_CH3_GPIO, &GPIO_InitStructure);
/* TIMx CH4 */
GPIO_InitStructure.Pin = TIMx_CH4_PIN;
GPIO_InitStructure.GPIO_Alternate = TIMx_CH4_AF;
GPIO_InitPeripheral(TIMx_CH4_GPIO, &GPIO_InitStructure);
The four pins and alternate numbers come from the TIMx_CH1_* to TIMx_CH4_* macros in inc/main.h, so check them together when changing boards.
2. The time base sets the PWM period. The counter clock is divided by SystemCoreClock / 16000000 to 16 MHz and the auto-reload value is 1200, so the PWM period is 1201 counts.
/* Compute the prescaler value */
PrescalerValue = (uint32_t)(SystemCoreClock / 16000000) - 1;
/* Time base configuration */
TIM_InitTimBaseStruct(&TIM_TimeBaseStructure);
TIM_TimeBaseStructure.Period = 1200;
TIM_TimeBaseStructure.Prescaler = PrescalerValue;
TIM_TimeBaseStructure.ClkDiv = TIM_CLK_DIV1;
TIM_TimeBaseStructure.CounterMode = TIM_CNT_MODE_UP;
TIM_InitTimeBase(TIMx, &TIM_TimeBaseStructure);
Change the PWM frequency through the divisor or Period; the duty cycle is set by the ratio of each channel compare value to Period.
3. Use PWM1 mode for the channels and enable preload. The four channels share the structure; for CH1 the PWM1 mode, output enable and polarity are written before the channel is enabled, and the output compare preload is enabled.
/* PWM1 Mode configuration: Channel1 */
TIM_InitOcStruct(&TIM_OCInitStructure);
TIM_OCInitStructure.OCMode = TIM_OCMODE_PWM1;
TIM_OCInitStructure.OutputState = TIM_OUTPUT_STATE_ENABLE;
TIM_OCInitStructure.Pulse = CCR1_Val;
TIM_OCInitStructure.OCPolarity = TIM_OC_POLARITY_HIGH;
TIM_InitOc1(TIMx, &TIM_OCInitStructure);
TIM_ConfigOc1Preload(TIMx, TIM_OC_PRE_LOAD_ENABLE);
Change the duty cycle of one channel through its CCRx_Val; with preload enabled a new compare value written at run time takes effect on the next update event.
4. Auto-reload preload and start. Finally the auto-reload preload is enabled so a change to Period also takes effect on an update event, and counting starts.
TIM_ConfigArPreload(TIMx, ENABLE);
/* TIMx enable counter */
TIM_Enable(TIMx, ENABLE);
With the auto-reload preload enabled, changing Period does not truncate the current period at once, which suits adjusting the PWM frequency at run time.
Corresponding source files: src/main.c, inc/main.h
5.20.3.16 TimeBasic6_BTIM_wakeup Basic timer STOP wake-up
Example directory: projects/n32g41x_EVAL/examples/TIM/TimeBasic6_BTIM_wakeup/
Enable the GPIO and BTIM1 clocks→Configure PA7 as a push-pull output→Configure EXTI line 20 as a rising edge and enable the BTIM1 interrupt→Configure the BTIM1 time base, select LSI as the clock source and enable the update interrupt→After a delay the main loop enters STOP and toggles PA7 again on each update wake-up
| Item | Source analysis |
|---|---|
| Function | BTIM1 uses LSI as its clock source and produces periodic update interrupts, which wake the MCU from STOP mode through EXTI line 20; after every wake-up the main loop toggles PA7 (LED D2 on the eval board), producing a blink. |
| Source files | src/main.c: main, RCC_Configuration, GPIO_Configuration, NVIC_Configuration and TIM_Configuration;inc/main.h: includes the GPIO, TIM, RCC, PWR, EXTI and delay related headers and declares those functions;src/n32g41x_it.c and inc/n32g41x_it.h: the BTIM1_IRQHandler interrupt service routine;readme.txt: function, environment and usage notes;MDK-ARM/ and EWARM/: the Keil and IAR projects. |
| Key configuration | PA7 uses GPIO_MODE_OUTPUT_PP. NVIC_Configuration sets EXTI_LINE20 to EXTI_Mode_Interrupt, EXTI_Trigger_Rising, enabled, and enables BTIM1_IRQn;TIM_Configuration uses Period 3200, Prescaler 0, ClkDiv TIM_CLK_DIV1, up counting and enables TIM_INT_UPDATE;main selects LSI as the BTIM1 clock source with RCC_ConfigBtim1Clk(RCC_BTIM1_CLKSEL_LSI). |
| Program and data path | main configures the clocks, GPIO and NVIC, calls TIM_Configuration to build the BTIM1 time base and enable the update interrupt, then selects the LSI source with RCC_ConfigBtim1Clk and starts counting;the main loop waits with SysTick_Delay_Ms(500), enters STOP with PWR_EnterSTOPMode (WFI entry), waits until the system clock is back on the PLL and toggles PA7 with GPIO_TogglePin;the update interrupt reaches BTIM1_IRQHandler through EXTI line 20 and clears both pending flags. |
| Main APIs | TIM_InitTimBaseStruct, TIM_InitTimeBase, TIM_ConfigInt, TIM_Enable, RCC_ConfigBtim1Clk, EXTI_InitPeripheral, EXTI_GetStatusFlag, EXTI_ClrITPendBit, PWR_EnterSTOPMode, RCC_GetSysclkSrc, GPIO_TogglePin, GPIO_InitPeripheral, SysTick_Delay_Ms |
| Verification | After building and downloading, reset and run: the LED on the eval board (D2, that is PA7) blinks periodically; the blink is driven by the STOP wake-up, and the system clock is LSI while STOP mode is entered. |
| Use note | In STOP mode the system clock is LSI and BTIM1 keeps running from the LSI clock source; EXTI line 20 (BTIM1) supports rising-edge triggering only. On the eval board PA9 and PA10 are connected to the NSLINK virtual UART by jumpers by default, so remove the jumpers when they are not used as a UART. Supported parts are N32G412x8L7, N32G412xBL7, N32G415x8L7 and N32G415xBL7; the development environment is KEIL MDK-ARM 5.34 or IAR EWARM 8.50.1. |
Core-code walkthrough and porting
The example routes the BTIM1 update interrupt to EXTI line 20, so the main loop enters STOP and is woken by that interrupt before toggling the LED pin once.
Data path: TIM_Configuration builds the BTIM1 time base and enables the update interrupt → RCC_ConfigBtim1Clk selects the LSI source → PWR_EnterSTOPMode enters STOP → the update interrupt reaches BTIM1_IRQHandler through EXTI line 20 → GPIO_TogglePin toggles PA7
1. Select the LSI clock source and start the timer. BTIM1 first builds its time base and update interrupt, then its clock source is switched to LSI; only with LSI or LSE as the clock source can the update interrupt wake the MCU from STOP.
/* Reconfig TIM6 */
TIM_Configuration();
RCC_ConfigBtim1Clk(RCC_BTIM1_CLKSEL_LSI);
/* TIM6 enable counter */
TIM_Enable(BTIM1, ENABLE);
When LSE is used as the wake-up source instead, change the clock selection macro here and make sure the corresponding clock is enabled.
2. Route the update interrupt to EXTI line 20. The EXTI line 20 flag is cleared before the interrupt is enabled, and the line is configured as a rising-edge interrupt; the BTIM1 interrupt channel and this EXTI line share the same vector.
/* Enable the BTIM1 Interrupt (IRQ20, shared with EXTI Line 20) */
EXTI_ClrStatusFlag(EXTI_LINE20);
EXTI_Struct.EXTI_Line = EXTI_LINE20;
EXTI_Struct.EXTI_Mode = EXTI_Mode_Interrupt;
EXTI_Struct.EXTI_Trigger = EXTI_Trigger_Rising;
EXTI_Struct.EXTI_LineCmd = ENABLE;
EXTI_InitPeripheral(&EXTI_Struct);
EXTI line 20 supports rising-edge triggering only, so the edge cannot be changed in software; do not configure it as falling-edge or both-edge when porting.
3. BTIM1 time base and update interrupt. The time base structure uses Period 3200 and Prescaler 0, and after it is built the update flag is cleared before the update interrupt is enabled, so a stale flag does not cause a spurious first interrupt.
/* Time base configuration */
TIM_InitTimBaseStruct(&TIM_TimeBaseStructure);
TIM_TimeBaseStructure.Period = 3200;
TIM_TimeBaseStructure.Prescaler = 0;
TIM_TimeBaseStructure.ClkDiv = TIM_CLK_DIV1;
TIM_TimeBaseStructure.CounterMode = TIM_CNT_MODE_UP;
TIM_InitTimeBase(BTIM1, &TIM_TimeBaseStructure);
/* Clear update interrupt flag before enabling */
TIM_ClrIntPendingBit(BTIM1, TIM_INT_UPDATE);
/* Enable BTIM1 update interrupt */
TIM_ConfigInt(BTIM1, TIM_INT_UPDATE, ENABLE);
With LSI as the clock source TIMx_CNT does not support writes, and Period together with Prescaler sets the wake-up period.
4. Enter STOP and wait for the wake-up. After a delay the main loop enters STOP and, once woken by the update interrupt, first waits for the system clock to switch back to the PLL before toggling the LED pin.
while (1)
{
SysTick_Delay_Ms(500);
/* Enter STOP mode */
PWR_EnterSTOPMode(PWR_STOPENTRY_WFI);
/* Wait PLL ready, check sysclk source */
while(RCC_GetSysclkSrc() != RCC_CFG_SCLKSTS_PLL)
{
if(--timeout == 0)
{
break;
}
}
GPIO_TogglePin(GPIOA, GPIO_PIN_7);
}
After the wake-up the system clock is LSI, so it must be switched back to the PLL before the code can keep running at the intended frequency; this wait loop carries a timeout and can be kept when porting.
5. Clear both flags in the interrupt. Once EXTI line 20 is confirmed set, the BTIM1 update flag is cleared first and then the EXTI pending bit; missing either one causes repeated interrupts.
if(EXTI_GetStatusFlag(EXTI_LINE20) != RESET)
{
TIM_ClrIntPendingBit(BTIM1, TIM_INT_UPDATE);
EXTI_ClrITPendBit(EXTI_LINE20);
}
Corresponding source files: src/main.c, src/n32g41x_it.c
5.20.3.17 TimeBasic_cc Output-compare timing
Example directory: projects/n32g41x_EVAL/examples/TIM/TimeBasic_cc/
Enable the GPIO and GTIM1 clocks→Configure PB0 to PB3 as push-pull outputs→Build the time base with an independent divider to 16 MHz and set the four channels to output compare timing mode→Enable the CC1 to CC4 interrupts and start the counter→On a compare match the interrupt toggles the matching pin and accumulates the compare value
| Item | Source analysis |
|---|---|
| Function | CH1 to CH4 of GTIM1 run in output compare timing mode and each one raises an interrupt when its compare value is reached; the interrupt toggles the matching PB pin and adds a fixed amount to the compare value, producing a square wave with a controllable period. |
| Source files | src/main.c: main, RCC_Configuration, GPIO_Configuration and NVIC_Configuration;inc/main.h: includes the GPIO, TIM, RCC and misc headers and declares those functions;src/n32g41x_it.c and inc/n32g41x_it.h: the GTIM1_IRQHandler interrupt service routine and the CCRx_Val accumulation;readme.txt: function, environment and usage notes;MDK-ARM/ and EWARM/: the Keil and IAR projects. |
| Key configuration | The timer is GTIM1 and PB0, PB1, PB2 and PB3 all use GPIO_MODE_OUTPUT_PP. Period is 0xFFFFFFFF and the time base Prescaler is 0, while TIM_ConfigPrescaler uses SystemCoreClock / 16000000 for the 16 MHz division with reload mode TIM_PSC_RELOAD_MODE_IMMEDIATE;the four channels use TIM_OCMODE_TIMING, output enabled and TIM_OC_POLARITY_HIGH, with Pulse of 40961, 27309, 13654 and 6826, and preload disabled. |
| Program and data path | main configures the clocks, GPIO and NVIC, builds the time base and sets the 16 MHz division with TIM_ConfigPrescaler, then sets the four channels to timing compare mode with TIM_InitOc1 to TIM_InitOc4;it enables the CC1 to CC4 interrupts with TIM_ConfigInt and starts with TIM_Enable;each compare match enters GTIM1_IRQHandler, which clears the flag, toggles the matching PB pin with GPIO_WriteBit, reads the compare value back with TIM_GetCapx and writes its sum with CCRx_Val using TIM_SetCmpx. |
| Main APIs | TIM_InitTimBaseStruct, TIM_InitTimeBase, TIM_ConfigPrescaler, TIM_InitOcStruct, TIM_InitOc1 to TIM_InitOc4, TIM_ConfigInt, TIM_Enable, TIM_GetIntStatus, TIM_GetCap1, TIM_SetCmp1, GPIO_WriteBit, GPIO_ReadOutputDataBit, GPIO_InitStruct, GPIO_InitPeripheral |
| Verification | Watch PB0 to PB3 with an oscilloscope or logic analyzer: each output toggles when its compare value is reached and the compare value is then accumulated; the toggle period is set by CCRx_Val with the 16 MHz counter clock. |
| Use note | On the eval board PA9 and PA10 are connected to the NSLINK virtual UART by jumpers by default; remove the jumpers when they are not used as a UART. Supported parts are N32G412x8L7, N32G412xBL7, N32G415x8L7 and N32G415xBL7; the development environment is KEIL MDK-ARM 5.34 or IAR EWARM 8.50.1. |
Core-code walkthrough and porting
The example uses an independent divider configuration to set the counter clock to 16 MHz, and the four output compare timing channels raise interrupts so software toggles the pins and advances the compare values.
Data path: GPIO_Configuration configures PB0 to PB3 as push-pull outputs → TIM_InitTimeBase and TIM_ConfigPrescaler set up the 16 MHz count → TIM_InitOc1 to TIM_InitOc4 select timing compare → GTIM1_IRQHandler toggles the PB pins and accumulates the compare values → the pins are observed on PB0 to PB3 with an oscilloscope
1. Configure the four pins as push-pull outputs first. The four pins are configured in one statement, and GPIO_MODE_OUTPUT_PP sets the output type used by the software toggling in the interrupt.
/* PB0, PB1, PB2, PB3 as output */
GPIO_InitStructure.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_3;
GPIO_InitStructure.GPIO_Mode = GPIO_MODE_OUTPUT_PP;
GPIO_InitPeripheral(GPIOB, &GPIO_InitStructure);
When moving to other pins, change the pin group and the port name together.
2. Time base and independent divider. The divider value for 16 MHz is computed first, Period is set to full scale in the time base, and the divider is then written with TIM_ConfigPrescaler in immediate reload mode.
/* Compute the prescaler value */
PrescalerValue = (uint16_t)(SystemCoreClock / 16000000) - 1;
/* Time base configuration */
TIM_InitTimBaseStruct(&TIM_TimeBaseStructure);
TIM_TimeBaseStructure.Period = 0xFFFFFFFF;
TIM_TimeBaseStructure.Prescaler = 0;
TIM_TimeBaseStructure.ClkDiv = TIM_CLK_DIV1;
TIM_TimeBaseStructure.CounterMode = TIM_CNT_MODE_UP;
TIM_InitTimeBase(GTIM1, &TIM_TimeBaseStructure);
/* Prescaler configuration */
TIM_ConfigPrescaler(GTIM1, PrescalerValue, TIM_PSC_RELOAD_MODE_IMMEDIATE);
The divider value sets the time resolution of the compare values; changing the 16 MHz divisor changes the toggle rate of all channels.
3. Use timing compare mode for the channels. The four channels share the structure; for CH1 the OCMode is TIM_OCMODE_TIMING, CCR1_Val is written before the channel is enabled, and preload is disabled.
/* Output Compare Timing Mode configuration: Channel1 */
TIM_InitOcStruct(&TIM_OCInitStructure);
TIM_OCInitStructure.OCMode = TIM_OCMODE_TIMING;
TIM_OCInitStructure.OutputState = TIM_OUTPUT_STATE_ENABLE;
TIM_OCInitStructure.Pulse = CCR1_Val;
TIM_OCInitStructure.OCPolarity = TIM_OC_POLARITY_HIGH;
TIM_InitOc1(GTIM1, &TIM_OCInitStructure);
TIM_ConfigOc1Preload(GTIM1, TIM_OC_PRE_LOAD_DISABLE);
Change the toggle rate of one channel through its CCRx_Val; with preload disabled a compare value written in the interrupt takes effect at once.
4. Enable the interrupts, start and toggle in the interrupt. The CC1 to CC4 interrupts are enabled and counting starts; each compare match enters GTIM1_IRQHandler, which clears the flag, toggles the PB pin and pushes the compare value forward by a fixed amount.
/* TIM IT enable */
TIM_ConfigInt(GTIM1, TIM_INT_CC1 | TIM_INT_CC2 | TIM_INT_CC3 | TIM_INT_CC4, ENABLE);
/* GTIM1 enable counter */
TIM_Enable(GTIM1, ENABLE);
if (TIM_GetIntStatus(GTIM1, TIM_INT_CC1) != RESET)
{
TIM_ClrIntPendingBit(GTIM1, TIM_INT_CC1);
/* Pin PB0 toggling */
GPIO_WriteBit(GPIOB, GPIO_PIN_0, (Bit_OperateType)(1 - GPIO_ReadOutputDataBit(GPIOB, GPIO_PIN_0)));
capture = TIM_GetCap1(GTIM1);
TIM_SetCmp1(GTIM1, capture + CCR1_Val);
}
The other three channels are branches written the same way with the channel and pin numbers increased; to change a pin, change the GPIO_PIN_x in the matching branch.
Corresponding source files: src/main.c, src/n32g41x_it.c
5.20.3.18 TimeBasic_update Update interrupt timing
Example directory: projects/n32g41x_EVAL/examples/TIM/TimeBasic_update/
Enable the GPIO and ATIM1 clocks→Configure PB0 as a push-pull output→Build the ATIM1 time base, write the prescaler and enable the update interrupt→Start the counter and toggle PB0 on every update interrupt
| Item | Source analysis |
|---|---|
| Function | ATIM1 enables its update interrupt, so every counter overflow produces an update event and the interrupt toggles PB0, forming a square wave with a fixed period. |
| Source files | src/main.c: main, RCC_Configuration, GPIO_Configuration, NVIC_Configuration and TIM_Configuration;inc/main.h: includes the GPIO, TIM, RCC and misc headers and declares those functions;src/n32g41x_it.c and inc/n32g41x_it.h: the ATIM1_UP_IRQHandler interrupt service routine;readme.txt: function, environment and usage notes;MDK-ARM/ and EWARM/: the Keil and IAR projects. |
| Key configuration | The ATIM1 clock comes from RCC_APB2_PERIPH_ATIM1;PB0 uses GPIO_MODE_OUTPUT_PP;the interrupt channel is ATIM1_UP_IRQn with preemption priority 1 and subpriority 0;Period is 65535, Prescaler is 0, ClkDiv is TIM_CLK_DIV1 and counting is up, with TIM_ConfigPrescaler writing value 0 and TIM_PSC_RELOAD_MODE_IMMEDIATE, and TIM_INT_UPDATE enabled. |
| Program and data path | main configures the clocks, GPIO and NVIC, calls TIM_Configuration to build the time base, write the prescaler, enable the update interrupt and start counting;every update event enters ATIM1_UP_IRQHandler, which clears the update flag and toggles PB0 with GPIO_WriteBit. |
| Main APIs | TIM_InitTimBaseStruct, TIM_InitTimeBase, TIM_ConfigPrescaler, TIM_ConfigInt, TIM_Enable, TIM_GetIntStatus, TIM_ClrIntPendingBit, GPIO_WriteBit, GPIO_ReadOutputDataBit, GPIO_InitStruct, GPIO_InitPeripheral |
| Verification | Watch PB0 with an oscilloscope or logic analyzer: while running PB0 toggles once per update period, so the square wave period is twice the update period and is set by Period with the ATIM1 counter clock. |
| Use note | On the eval board PA9 and PA10 are connected to the NSLINK virtual UART by jumpers by default; remove the jumpers when they are not used as a UART. Supported parts are N32G412x8L7, N32G412xBL7, N32G415x8L7 and N32G415xBL7; the development environment is KEIL MDK-ARM 5.34 or IAR EWARM 8.50.1. |
Core-code walkthrough and porting
The example drives the PB0 toggle from the ATIM1 update interrupt, with no peripheral other than the time base and the interrupt enable involved.
Data path: RCC_Configuration enables the ATIM1 clock → TIM_Configuration builds the time base, writes the prescaler and enables the update interrupt → TIM_Enable starts counting → the update event enters ATIM1_UP_IRQHandler → GPIO_WriteBit toggles PB0
1. Configure PB0 as a push-pull output. Only one pin is used to output the square wave, so a plain push-pull output is enough and the software toggling in the interrupt produces the waveform.
/* PB0 as output */
GPIO_InitStructure.Pin = GPIO_PIN_0;
GPIO_InitStructure.GPIO_Mode = GPIO_MODE_OUTPUT_PP;
GPIO_InitPeripheral(GPIOB, &GPIO_InitStructure);
2. ATIM1 sits on APB2. The advanced timer ATIM1 takes its clock from the APB2 bus, unlike a general timer on APB1, so change the macro according to the bus when another timer is used.
/* Enable GPIO clock */
RCC_EnableAHBPeriphClk(RCC_AHB_PERIPH_GPIO, ENABLE);
/* Enable ATIM1 clock */
RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_ATIM1, ENABLE);
3. Time base, prescaler and update interrupt. The time base uses Period 65535 and Prescaler 0; after it is built TIM_ConfigPrescaler writes the divider in immediate reload mode, then the update interrupt is enabled and counting starts.
/* Time base configuration */
TIM_InitTimBaseStruct(&TIM_TimeBaseStructure);
TIM_TimeBaseStructure.Period = 65535;
TIM_TimeBaseStructure.Prescaler = 0;
TIM_TimeBaseStructure.ClkDiv = TIM_CLK_DIV1;
TIM_TimeBaseStructure.CounterMode = TIM_CNT_MODE_UP;
TIM_InitTimeBase(ATIM1, &TIM_TimeBaseStructure);
/* Prescaler configuration */
TIM_ConfigPrescaler(ATIM1, PrescalerValue, TIM_PSC_RELOAD_MODE_IMMEDIATE);
/* ATIM1 enable update irq */
TIM_ConfigInt(ATIM1, TIM_INT_UPDATE, ENABLE);
/* ATIM1 enable counter */
TIM_Enable(ATIM1, ENABLE);
Change the square wave frequency through Period and the divider; the update interrupt fires when the counter overflows.
4. Match the interrupt vector to the timer. The update interrupt channel of the advanced timer is ATIM1_UP_IRQn, and the preemption and subpriority are written together here.
/* Enable the ATIM1 Interrupt */
NVIC_InitStructure.NVIC_IRQChannel = ATIM1_UP_IRQn;
NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 1;
NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
NVIC_Init(&NVIC_InitStructure);
5. Toggle PB0 in the interrupt. Once the update flag is confirmed set it is cleared first, then PB0 is toggled by reading back the output level and inverting it.
if (TIM_GetIntStatus(ATIM1, TIM_INT_UPDATE) != RESET)
{
TIM_ClrIntPendingBit(ATIM1, TIM_INT_UPDATE);
/* PB0 toggle */
GPIO_WriteBit(GPIOB, GPIO_PIN_0, (Bit_OperateType)(1 - GPIO_ReadOutputDataBit(GPIOB, GPIO_PIN_0)));
}
Corresponding source files: src/main.c, src/n32g41x_it.c
5.20.4 Notes and troubleshooting
| Scenario | Check & action | Source |
|---|---|---|
| Update event and preload | For PWM or output-compare preload to take effect, the corresponding TIMx_CCMODx.OCxPEN must be set, and ARR preload is controlled by TIMx_CTRL1.ARPEN;preload values move to the shadow registers only on an update event, so an update must be generated in software before the counter starts to reset all registers. |
User manual |
| Updating compare values at run time | With preload registers disabled, TIMx_CCDATx can be written at any time to update the output waveform;with preload enabled, the written value reaches the shadow register only on the next update event. |
User manual |
| Center-aligned mode | Switching from edge-aligned to center-aligned is not allowed while the counter runs, and the counter must not be written in center-aligned mode; do not change TIMx_CTRL1.DIR and CAMSEL at the same time. |
User manual |
| Channel limit of PWM input mode | PWM input mode can be used with the TIMx_CH1 and TIMx_CH2 signals only, because only TI1FP1 and TI2FP2 are connected to the slave-mode controller. |
User manual |
| Conditions for BTIM1 to wake up STOP | BTIM1 can wake up STOP mode through its update interrupt (redirected to EXTI 20) only when its clock source is configured as LSI or LSE. | User manual |
| Writing the counter with LSI as clock source | When the clock source is configured as LSI, TIMx_CNT does not support writes. |
User manual |
| Mutual exclusion of encoder mode and external clock | Encoder mode and external clock mode 2 are incompatible and cannot be selected at the same time. | User manual |
The N32G412 and N32G415 series errata sheet V1.0.0 (2026.6.30) lists a single row for revision A chips with an empty errata link column, and gives no TIM related entries.