AI FAE Platform2. Product and Kit Overview
This chapter describes the core and peripheral configuration of the N32G41x series, and the parts and scale of Nsing.N32G41x_Library.1.1.0. Capability items are taken from the NSING Technology official model pages and the user manual, and the quantity statistics are taken from the SDK file tree. This chapter does not cover register addresses, electrical limits or timing parameters; those follow the datasheet and the user manual.
2.1 Core and Peripheral Overview
The N32G41x series contains the N32G412 and N32G415 sub-families. The table lists the maximum configuration of the series by sub-family.
| Item | N32G412 | N32G415 |
|---|---|---|
| Core | Arm Cortex-M4, single-cycle hardware multiplier, DSP instructions, 1 KB instruction cache | Same as N32G412 |
| Max frequency | 80 MHz, 100 DMIPS | 96 MHz, 120 DMIPS |
| Bus clock limit | AHB 80 MHz, APB1 40 MHz, APB2 80 MHz | AHB 96 MHz, APB1 48 MHz, APB2 96 MHz |
| Memory | Up to 128 KB Flash, 24 KB SRAM | Same as N32G412 |
| GPIO | Up to 60 | Up to 61 |
| Analog | Two 12-bit 2 Msps ADCs, four rail-to-rail OPAMPs, three comparators, internal 2.4 V reference | Same as N32G412, plus support for an external reference voltage input |
| Communication | Four USARTs, two SPIs (SPI1 can be remapped to I2S), two I2Cs, one CAN 2.0A/B | Same as N32G412 |
| Timers | ATIM1 and ATIM2 advanced timers, GTIM1 (32-bit) and GTIM2, GTIM3, GTIM4 general timers, BTIM1 and BTIM2 basic timers, WWDG, IWDG | Same as N32G412 |
| Other peripherals | Seven-channel DMA, RTC, CRC16 and CRC32 | Same as N32G412 |
| Reset and supply monitoring | Power-on reset, brown-out reset, external pin reset, watchdog reset, programmable PVD voltage detection | Same as N32G412 |
| Debug and boot | SWD debug interface; Bootloader supporting USART, I2C and CAN |
Same as N32G412 |
| Security and identification | Flash write protection WRP, read protection RDP (L0 to L2), secure boot and secure update, external clock failure detection, 96-bit UID, 128-bit UCID | Same as N32G412 |
| Operating conditions | 2.0 V to 5.5 V, -40 °C to +105 °C, ESD ±4 KV (HBM) and ±2 KV (CDM) | Same as N32G412 |
The table shows the maximum configuration of each sub-family; the memory size, package pin count and peripheral count of a specific model follow the corresponding datasheet. The two sub-families differ in the maximum clock frequency, the bus clock limits, the GPIO count, and the external independent reference voltage source supported by the N32G415; all other peripheral types and counts are identical. The default system clock configuration and bus prescalers are described at the end of section 2.2.
2.2 SDK at a Glance
Nsing.N32G41x_Library.1.1.0 consists of the standard peripheral driver library, CMSIS device support, the FreeRTOS middleware, example projects and board support. Its scale is as follows:
- 20 driver modules
- 656 public APIs
- 22 example categories
- 101 examples
| Component | Content |
|---|---|
| Standard peripheral driver library | Each driver module is a .h / .c pair;the public APIs are all function declarations in the header |
| CMSIS device support | Device header, system clock initialisation, Keil / IAR / GCC startup files and the GCC linker script |
| FreeRTOS middleware | FreeRTOS Kernel V11.3.1 sources and the Cortex-M port layer under Middlewares/ |
| Example projects | Organised by peripheral category; each example provides both a Keil MDK-ARM and an IAR EWARM project |
| Board support | LED and key pin definitions, debug UART log output and SysTick delays |
Counting rules: a driver module is a driver unit under firmware/n32g41x_std_periph_driver, and a public API is a function declared in these headers that can be called directly from a user project. Examples are counted as example entries containing an MDK-ARM, EWARM or GCC build project; paired sub-projects that share a description file in the parent directory count as one, and shared code directories without a project are not counted. The mapping between the DBG module, the NVIC category and the Cortex-M4 category is given in the Peripherals and Examples chapter.
After reset the system clock uses the internal high-speed clock HSI multiplied by the PLL: 80 MHz for the N32G412 and 96 MHz for the N32G415. The clock source and frequency are selected by the SYSCLK_SRC and SYSCLK_FREQ macros in system_n32g41x.c, and the available options are defined in system_n32g41x.h. The bus prescalers follow from the system clock, so after changing the system clock you must re-check the clock enable and prescaler configuration of each peripheral.