5.13 IWDG Guide

The example prepares the LSI clock and the debug-halt behaviour of the watchdog first, then configures the timeout and starts the watchdog, and finally feeds it in the main loop and reads the reset flag.

Data path: DBG_ConfigPeriph and RCC_EnableLsi enable LSI → IWDG_WriteConfig, IWDG_SetPrescalerDiv, IWDG_CntReload write PREDIV and RELV → IWDG_Enable starts the counter → IWDG_ReloadKey reloads the counter in the while(1) loop → a timeout sets RCC_CTRLSTS_FLAG_IWDGRSTF → LedOn lights LED1

1. Prepare the LSI clock and the debug-halt behaviour. The watchdog is driven by the LSI, so main first stops the IWDG counter while the core is halted and then enables the LSI and polls its ready flag, so that the timeout configuration is based on a settled clock.

    DBG_ConfigPeriph(DBG_IWDG_STOP, ENABLE);

    /* Enable LSI Clock */
    RCC_EnableLsi(ENABLE);
    while (RCC_GetFlagStatus(RCC_CTRL_FLAG_LSIRDF) != SET)
    {
    }

To keep the watchdog counting during a debug halt, replace DBG_IWDG_STOP with another peripheral macro or drop this call; the LSI ready wait feeds the timeout calculation and should not be removed.

2. Configure the prescaler and reload value and start the watchdog. This part disables the write protection of PREDIV and RELV, sets the prescaler to LSI/32 and derives a reload value of about 250 ms from LsiFreq / 128, then reloads the counter and starts the watchdog.

    /* IWDG timeout equal to 250 ms (the timeout may varies due to LSI frequency
       dispersion) */
    /* Enable write access to IWDG_PR and IWDG_RLR registers */
    IWDG_WriteConfig(IWDG_WRITE_ENABLE);

    /* IWDG counter clock: LSI/32 */
    IWDG_SetPrescalerDiv(IWDG_PRESCALER_DIV32);

    /* Set counter reload value to obtain 250ms IWDG TimeOut.
       Counter Reload Value = 250ms/IWDG counter clock period
                            = 250ms / (LSI/32)
                            = 0.25s / (LsiFreq/32)
                            = LsiFreq/(32 * 4)
                            = LsiFreq/128 */
    log_debug("LsiFreq is: %d\n", LsiFreq);

    IWDG_CntReload(LsiFreq / 128);
    /* Reload IWDG counter */
    IWDG_ReloadKey();

    /* Enable IWDG (the LSI oscillator will be enabled by hardware) */
    IWDG_Enable();

The timeout follows from both the prescaler and the reload value; changing the prescaler means updating the LsiFreq / 128 conversion and making sure LsiFreq matches the actual LSI frequency.

3. Feed the watchdog in the main loop. The loop toggles LED3 to show the program is running and then reloads the counter after a 249 ms delay (below the 250 ms timeout), so the watchdog is never triggered.

    while (1)
    {
        /* Toggle LED3 */
        LedBlink(LED3_PORT, LED3_PIN);
        /* Insert 249 ms delay (exceeds IWDG timeout -> reset) */
        SysTick_Delay_Ms(249);
        /* Reload IWDG counter */
        IWDG_ReloadKey();
    }

The feed interval must stay below the timeout derived from the reload value; setting the SysTick_Delay_Ms argument to 251 or more triggers a reset and can be used to check the timeout.

4. Tell the reset source from the reset flag. After a reset the code reads RCC_CTRLSTS_FLAG_IWDGRSTF; when it is set the reset came from IWDG, so LED1 is lit and the reset flags are cleared, otherwise LED1 stays off.

    /* Check if the system has resumed from IWDG reset */
    if (RCC_GetFlagStatus(RCC_CTRLSTS_FLAG_IWDGRSTF) != RESET)
    {
        /* IWDGRST flag set */
        LedOn(LED1_PORT, LED1_PIN);
        log_info("reset by IWDG\n");
        /* Clear reset flags */
        RCC_ClearResetFlag();
    }
    else
    {
        /* IWDGRST flag is not set */
        LedOff(LED1_PORT, LED1_PIN);
    }

RCC_ClearResetFlag clears all reset flags, so when several reset sources must be told apart it also wipes the others; LED1 staying on after a reset means an IWDG reset has already occurred.

Corresponding source files: src/main.c, inc/main.h, projects/n32g41x_EVAL/bsp/inc/n32g41x_stb.h