5.17 RCC Guide

This chapter describes the file composition and the 86 public functions of the RCC driver in the N32G41x standard peripheral library: reset, the configuration of the oscillators and the PLL, the system clock and bus prescalers, peripheral clock enable and reset, the MCO clock output, the clock security system, and interrupt and flag management, together with one example, RCC_ClockConfig. Read the clock tree, the oscillator characteristics and the register definitions together with the “Reset and clock control (RCC)” chapter of the user manual, and take the errata sheet as the authority on known chip issues.

5.17.1 Related files

Relative path	Purpose
`firmware/n32g41x_std_periph_driver/inc/n32g41x_rcc.h`	Defines the `RCC_ClocksType` structure and the macros for clock sources, prescalers, MCO, the clock security system, interrupts and flags, and declares 86 public functions in the seventeen sections of the header
`firmware/n32g41x_std_periph_driver/src/n32g41x_rcc.c`	Implements those 86 functions: enabling and calibrating the oscillators, configuring the PLL, the system clock and the bus prescalers, the peripheral clock enable and reset, the peripheral, timer and filter clock sources, the MCO output, the clock security system, EMC and Glitch detection, and interrupt and flag management
`projects/n32g41x_EVAL/examples/RCC/`	RCC example root directory, containing 1 example: RCC_ClockConfig
`projects/n32g41x_EVAL/examples/RCC/RCC_ClockConfig/`	Composition of that example: `MDK-ARM/`, `EWARM/`, `inc/`, `src/`, `readme.txt`
`projects/n32g41x_EVAL/bsp/`	Board support files used by the example: serial log output and millisecond delay

5.17.2 API reference

The following 86 public functions are listed in the declaration order of n32g41x_rcc.h in 17 groups; each entry gives a summary and the original comment above the function in n32g41x_rcc.c.

Reset

RCC_DeInit

HSI configuration

RCC_EnableHsi, RCC_SetHsiCalibValue, RCC_WaitHsiStable

HSE configuration

RCC_ConfigHse, RCC_ConfigHseReadyDly, RCC_WaitHseStable

LSI configuration

RCC_EnableLsi, RCC_SetLsiCalibValue, RCC_WaitLsiStable

LSE configuration

RCC_ConfigLse, RCC_WaitLseStable, RCC_EnableLseNim, RCC_ConfigLseGlitchFilter, RCC_ConfigLseBuffOpt, RCC_ConfigLseBiasTrim, RCC_ConfigLseDrvTrim

PLL configuration

RCC_ConfigPll, RCC_EnablePll, RCC_EnablePllBypass, RCC_EnablePllSysclkDiv

System clock and bus prescaler configuration

RCC_ConfigSysclk, RCC_GetSysclkSrc, RCC_ConfigHclk, RCC_ConfigPclk1, RCC_ConfigPclk2, RCC_GetClocksFreqValue

Peripheral clock enable and reset

RCC_EnableAHBPeriphClk, RCC_EnableAPB1PeriphClk, RCC_EnableAPB2PeriphClk, RCC_EnableAHBPeriphReset, RCC_EnableAPB1PeriphReset, RCC_EnableAPB2PeriphReset

Peripheral clock source configuration

RCC_ConfigAdc1mClk, RCC_ConfigAdcSysclk, RCC_ConfigI2SClk, RCC_ConfigUsart1Clk, RCC_ConfigUsart4Clk, RCC_ConfigRTCClk, RCC_ConfigLowPowerClk

Timer clock source configuration

RCC_ConfigAtim1Clk, RCC_ConfigAtim2Clk, RCC_ConfigGtim1Clk, RCC_ConfigGtim2Clk, RCC_ConfigGtim3Clk, RCC_ConfigGtim4Clk, RCC_ConfigBtim1Clk

Timer and IO filter clock divider configuration

RCC_ConfigIOFilter, RCC_ConfigATIM1Filter, RCC_ConfigATIM2Filter, RCC_ConfigGTIM1Filter, RCC_ConfigGTIM2Filter, RCC_ConfigGTIM3Filter, RCC_ConfigGTIM4Filter

MCO output configuration

RCC_ConfigMco, RCC_ConfigMcoClkPre

Clock security system

RCC_EnableHSEClockSecuritySystem, RCC_EnableLSEClockSecuritySystem, RCC_EnableHSECaptureRequest, RCC_EnableLSECaptureRequest

EMC detection and protection

RCC_EnableEMCDetect, RCC_ConfigEMCDetectLevel, RCC_EnableEMCReset, RCC_EnableEMCSwitch, RCC_EnableEMCGBInt, RCC_EnableEMCGBNInt

Glitch detection and protection

RCC_EnableGlitchDetect, RCC_ConfigGlitchDetectLevel, RCC_EnableGlitchReset, RCC_EnableGlitchSwitch, RCC_EnableGlitchInt, RCC_EnableM4LockupReset

Power step configuration

RCC_EnablePwrUpStep, RCC_EnablePwrDownStep, RCC_ConfigPwrUpStepWidth, RCC_ConfigPwrDownStepWidth, RCC_EnablePStepSf, RCC_PStepSfDiv, RCC_ClearPwrDownStepFlag, RCC_GetPwrDownStepFlag, RCC_GetPwrStepFsm

Interrupt and flag management

RCC_ConfigInt, RCC_GetIntStatus, RCC_ClrIntPendingBit, RCC_GetFlagStatus, RCC_ClearResetFlag

void RCC_DeInit(void)Reset the RCC registers.

Source comment

name    RCC_DeInit.
fun     Reset the RCC registers.
param   none
return  none

void RCC_EnableHsi(FunctionalState Cmd)Enables the Internal High Speed oscillator (HSI).

Source comment

name    RCC_EnableHsi.
fun     Enables the Internal High Speed oscillator (HSI).
param   Cmd:
          - ENABLE
          - DISABLE
return  none
note   HSI can not be stopped if it is used directly or through the PLL as system clock.

void RCC_SetHsiCalibValue(uint16_t calibration_value)Adjusts the Internal High Speed oscillator (HSI) calibration value.

Source comment

name    RCC_SetHsiCalibValue.
fun     Adjusts the Internal High Speed oscillator (HSI) calibration value.
param   calibration_value(the calibration trimming value):
        This parameter must be a number between 0 and 0x1FF
return  none

ErrorStatus RCC_WaitHsiStable(void)Waits for HSI start-up.

Source comment

name    RCC_WaitHsiStable.
fun     Waits for HSI start-up.
param   none
return  ErrorStatus:
         - SUCCESS    HSI oscillator is stable and ready to use
         - ERROR      HSI oscillator not yet ready

void RCC_ConfigHse(uint32_t RCC_HSE)Configures the External High Speed oscillator (HSE).

Source comment

name    RCC_ConfigHse.
fun     Configures the External High Speed oscillator (HSE).
param   RCC_HSE :
          - RCC_HSE_DISABLE    HSE oscillator OFF
          - RCC_HSE_ENABLE     HSE oscillator ON
          - RCC_HSE_BYPASS     HSE oscillator bypassed with external clock
return  none:
note    HSE can not be stopped if it is used directly or through the PLL as system clock

void RCC_ConfigHseReadyDly(uint32_t hse_dlydiv)Configures the HSE RDF Time

Source comment

name    RCC_ConfigHseReadyDly.
fun     Configures the HSE RDF Time
param   hse_dlydiv(HSE RDF delay value):
         - RCC_HSERDFDIV_1MS
         - RCC_HSERDFDIV_2MS
         - RCC_HSERDFDIV_3MS
         - RCC_HSERDFDIV_4MS
         - RCC_HSERDFDLY_128HSE
return  none

ErrorStatus RCC_WaitHseStable(void)Waits for HSE start-up.

Source comment

name    RCC_WaitHseStable.
fun     Waits for HSE start-up.
param   none
return  ErrorStatus:
         - SUCCESS    HSE oscillator is stable and ready to use
         - ERROR      HSE oscillator not yet ready

void RCC_EnableLsi(FunctionalState Cmd)Enables the LSI.

Source comment

name    RCC_EnableLsi.
fun     Enables the LSI.
param   Cmd:
          - ENABLE
          - DISABLE
return  none

void RCC_SetLsiCalibValue(uint16_t calibration_value)Adjusts the Internal Low Speed oscillator (LSI) calibration value.

Source comment

name    RCC_SetLsiCalibValue.
fun     Adjusts the Internal Low Speed oscillator (LSI) calibration value.
param   calibration_value(the calibration trimming value):
        This parameter must be a number between 0 and 0x3F
return  none

ErrorStatus RCC_WaitLsiStable(void)Waits for LSI start-up.

Source comment

name    RCC_WaitLsiStable.
fun     Waits for LSI start-up.
param   none
return  ErrorStatus:
         - SUCCESS    LSI oscillator is stable and ready to use
         - ERROR      LSI oscillator not yet ready

void RCC_ConfigLse(uint32_t RCC_LSE)Configures the External Low Speed oscillator (LSE).

Source comment

name    RCC_ConfigLse.
fun     Configures the External Low Speed oscillator (LSE).
param   RCC_LSE :
          - RCC_LSE_DISABLE    LSE oscillator OFF
          - RCC_LSE_ENABLE     LSE oscillator ON
          - RCC_LSE_BYPASS     LSE oscillator bypassed with external clock
return  none.
note none.

ErrorStatus RCC_WaitLseStable(void)Waits for LSE start-up.

Source comment

name    RCC_WaitLseStable.
fun     Waits for LSE start-up.
param   none
return  ErrorStatus:
         - SUCCESS    LSE oscillator is stable and ready to use
         - ERROR      LSE oscillator not yet ready

void RCC_EnableLseNim(FunctionalState Cmd)LSE noise immunity enable.

Source comment

name    RCC_EnableLseNim.
fun     LSE noise immunity enable.
param   Cmd:
          - ENABLE
          - DISABLE
return  none.

void RCC_ConfigLseGlitchFilter(uint32_t lsegliterflit)Configure LSE glitch filter.

Source comment

name    RCC_ConfigLseGlitchFilter.
fun     Configure LSE glitch filter.
param   lse glitch filter select for  ad_lse_clkout
          - RCC_LSE_GLITCHFILTER_25ns
          - RCC_LSE_GLITCHFILTER_50ns
          - RCC_LSE_GLITCHFILTER_100ns
          - RCC_LSE_GLITCHFILTER_250ns
          - 0 : no glitch filter
return  none

void RCC_ConfigLseBuffOpt(uint32_t lsebuffopt)Configure LSE buffer trimming signal.

Source comment

name    RCC_ConfigLseBuffOpt.
fun     Configure LSE buffer trimming signal.
param   lsebuffopt (lse buffer trimming)
return  none

void RCC_ConfigLseBiasTrim(uint32_t LseBiasTrim)Configure lse bias trimming signal.

Source comment

name    RCC_ConfigLseBiasTrim.
fun     Configure lse bias trimming signal.
param   LseBiasTrim (lse bias trimming)
return  none

void RCC_ConfigLseDrvTrim(uint32_t lsedrvtrim)Configure LSE core trimming signal.

Source comment

name    RCC_ConfigLseDrvTrim.
fun     Configure LSE core trimming signal.
param   lsedrvtrim (lse drv trimming)
return  none

void RCC_ConfigPll(uint32_t PLL_source, uint32_t PLL_inpre, uint32_t PLL_mul, uint32_t PLL_od)Configures the PLL clock source and multiplication factor.

Source comment

name    RCC_ConfigPll.
fun     Configures the PLL clock source and multiplication factor.
param   PLL_source(PLL entry clock source):
          - RCC_PLL_SRC_HSI         HSI oscillator clock selected as PLL clock entry
          - RCC_PLL_SRC_HSE         HSE oscillator clock selected as PLL clock entry
param   PLL_inpre(PLL input divider):
          - 1 ~ 63(for div 1 ~ div 63)
param   PLL_mul(PLL multiplication factor):
          - 2 ~ 127(for mul 2 ~ mul 127)
param   PLL_od(PLL OD):
          - RCC_PLL_OD_DIV_1
          - RCC_PLL_OD_DIV_2
return  none
note    This function must be used only when the PLL is disabled.
note    Fin frequency requirement is in the range of 8MHz ~ 32MHz,
        Fin/PLL_inpre frequency requirement is in the range of 8MHz ~ 32MHz,
        Fvco(=Fin/PLL_inpre*PLL_mul) frequency requirement is in the range of 96MHz ~ 160MHz,
        Fout(=Fvco/PLL_od) frequency requirement is in the range of 64MHz ~ 160MHz.

Use note: Write the clock source and multiplier with this function first, then enable the PLL with RCC_EnablePll; these parameters cannot be changed while the PLL is active.

void RCC_EnablePll(FunctionalState Cmd)Enables the PLL.

Source comment

name    RCC_EnablePll.
fun     Enables the PLL.
param   Cmd:
          - ENABLE
          - DISABLE
return  none

void RCC_EnablePllBypass(FunctionalState Cmd)Enables the PLL Bypass.

Source comment

name    RCC_EnablePllBypass
fun     Enables the PLL Bypass.
param   Cmd:
          - ENABLE
          - DISABLE
return  none.

Use note: In bypass mode the PLL input clock goes straight to the output, so confirm that this input clock is already stable before switching.

void RCC_EnablePllSysclkDiv(FunctionalState Cmd)Configure whether to enable Pll Clock Output Div2 to sysclk.

Source comment

name    RCC_EnablePllSysclkDiv.
fun     Configure whether to enable Pll Clock Output Div2 to sysclk.
param   Cmd:
          - ENABLE
          - DISABLE
return  none.

Use note: This bit selects whether the PLL output is divided by two; clear it before enabling the PLL and configure it only after the PLL is ready.

void RCC_ConfigSysclk(uint32_t sysclk_source)Configures the system clock (SYSCLK).

Source comment

name    RCC_ConfigSysclk.
fun     Configures the system clock (SYSCLK).
param   sysclk_source(clock source used as system clock):
          - RCC_SYSCLK_SRC_HSI       HSI selected as system clock
          - RCC_SYSCLK_SRC_HSE       HSE selected as system clock
          - RCC_SYSCLK_SRC_PLL      PLL selected as system clock
return  none

uint32_t RCC_GetSysclkSrc(void)Returns the clock source used as system clock.

Source comment

name    RCC_GetSysclkSrc.
fun     Returns the clock source used as system clock.
param   none
return  (The clock source used as system clock):
          - RCC_SYSCLK_STS_HSI       HSI selected as system clock
          - RCC_SYSCLK_STS_HSE       HSE selected as system clock
          - RCC_SYSCLK_STS_PLL       PLL selected as system clock

void RCC_ConfigHclk(uint32_t sysclk_div)Configures the AHB clock (HCLK).

Source comment

name    RCC_ConfigHclk.
fun     Configures the AHB clock (HCLK).
param   sysclk_div(AHB clock is derived from the system clock (SYSCLK)):
          - RCC_SYSCLK_DIV1      AHB clock = SYSCLK
          - RCC_SYSCLK_DIV2      AHB clock = SYSCLK/2
          - RCC_SYSCLK_DIV4      AHB clock = SYSCLK/4
          - RCC_SYSCLK_DIV8      AHB clock = SYSCLK/8
          - RCC_SYSCLK_DIV16     AHB clock = SYSCLK/16
          - RCC_SYSCLK_DIV64     AHB clock = SYSCLK/64
          - RCC_SYSCLK_DIV128    AHB clock = SYSCLK/128
return  none

void RCC_ConfigPclk1(uint32_t RCC_HCLK)Configures the Low Speed APB clock (PCLK1).

Source comment

name    RCC_ConfigPclk1.
fun     Configures the Low Speed APB clock (PCLK1).
param   RCC_HCLK(APB1 clock is derived from the AHB clock (HCLK)):
          - RCC_HCLK_DIV1     APB1 clock = HCLK
          - RCC_HCLK_DIV2     APB1 clock = HCLK/2
          - RCC_HCLK_DIV4     APB1 clock = HCLK/4
          - RCC_HCLK_DIV8     APB1 clock = HCLK/8
          - RCC_HCLK_DIV16    APB1 clock = HCLK/16
return  none

void RCC_ConfigPclk2(uint32_t RCC_HCLK)Configures the High Speed APB clock (PCLK2).

Source comment

name    RCC_ConfigPclk2.
fun     Configures the High Speed APB clock (PCLK2).
param   RCC_HCLK(APB2 clock is derived from the AHB clock (HCLK)):
          - RCC_HCLK_DIV1     APB2 clock = HCLK
          - RCC_HCLK_DIV2     APB2 clock = HCLK/2
          - RCC_HCLK_DIV4     APB2 clock = HCLK/4
          - RCC_HCLK_DIV8     APB2 clock = HCLK/8
          - RCC_HCLK_DIV16    APB2 clock = HCLK/16
return  none

void RCC_GetClocksFreqValue(RCC_ClocksType *RCC_Clocks)Returns the frequencies of different on chip clocks.

Source comment

name    RCC_GetClocksFreqValue.
fun     Returns the frequencies of different on chip clocks.
param   RCC_Clocks pointer to a RCC_ClocksType structure which will hold
        the clocks frequencies.
return  none

Use note: The result is computed from the current RCC_CFG setting and the HSI_VALUE and HSE_VALUE macros, so update those macros together with the crystal.

void RCC_EnableAHBPeriphClk(uint32_t AHB_periph, FunctionalState Cmd)Enables the AHB peripheral clock.

Source comment

name    RCC_EnableAHBPeriphClk.
fun     Enables the AHB peripheral clock.
param   AHB_periph (AHB peripheral to gates its clock):
          - RCC_AHB_PERIPH_ADC2
          - RCC_AHB_PERIPH_ADC1
          - RCC_AHB_PERIPH_CRC
          - RCC_AHB_PERIPH_GPIO
          - RCC_AHB_PERIPH_DMA
param   Cmd:
          - ENABLE
          - DISABLE
return  none

void RCC_EnableAPB1PeriphClk(uint32_t APB1_periph, FunctionalState Cmd)Enables the Low Speed APB1 peripheral clock.

Source comment

name    RCC_EnableAPB1PeriphClk.
fun     Enables the Low Speed APB1 peripheral clock.
param   APB1_periph (APB1 peripheral to gates its clock):
          - RCC_APB1_PERIPH_OPAMP
          - RCC_APB1_PERIPH_CAN
          - RCC_APB1_PERIPH_I2C2
          - RCC_APB1_PERIPH_I2C1
          - RCC_APB1_PERIPH_USART3
          - RCC_APB1_PERIPH_USART2
          - RCC_APB1_PERIPH_WWDG
          - RCC_APB1_PERIPH_RTC
          - RCC_APB1_PERIPH_COMPFILT
          - RCC_APB1_PERIPH_COMP
          - RCC_APB1_PERIPH_BTIM2
          - RCC_APB1_PERIPH_BTIM1
          - RCC_APB1_PERIPH_GTIM4
          - RCC_APB1_PERIPH_GTIM3
          - RCC_APB1_PERIPH_GTIM2
          - RCC_APB1_PERIPH_GTIM1
param   Cmd:
          - ENABLE
          - DISABLE
return none.

void RCC_EnableAPB2PeriphClk(uint32_t APB2_periph, FunctionalState Cmd)Enables the High Speed APB2 peripheral clock.

Source comment

name    RCC_EnableAPB2PeriphClk.
fun     Enables the High Speed APB2 peripheral clock.
param   APB2_periph (APB2 peripheral to gates its clock):
          - RCC_APB2_PERIPH_SPI2
          - RCC_APB2_PERIPH_USART4
          - RCC_APB2_PERIPH_USART1
          - RCC_APB2_PERIPH_ATIM2
          - RCC_APB2_PERIPH_SPI1
          - RCC_APB2_PERIPH_ATIM1
param   Cmd:
          - ENABLE
          - DISABLE
return none.

void RCC_EnableAHBPeriphReset(uint32_t AHB_periph)AHB peripheral reset.

Source comment

name    RCC_EnableAHBPeriphReset.
fun     AHB peripheral reset.
param   AHB_periph specifies the AHB peripheral to reset.
          - RCC_AHB_PERIPH_ADC2
          - RCC_AHB_PERIPH_ADC1
          - RCC_AHB_PERIPH_GPIO
return none.

void RCC_EnableAPB1PeriphReset(uint32_t APB1_periph)Low Speed APB1 peripheral reset.

Source comment

name    RCC_EnableAPB1PeriphReset.
fun     Low Speed APB1 peripheral reset.
param   APB1_periph specifies the APB1 peripheral to reset.
          - RCC_APB1_PERIPH_OPAMP
          - RCC_APB1_PERIPH_CAN
          - RCC_APB1_PERIPH_I2C2
          - RCC_APB1_PERIPH_I2C1
          - RCC_APB1_PERIPH_USART3
          - RCC_APB1_PERIPH_USART2
          - RCC_APB1_PERIPH_WWDG
          - RCC_APB1_PERIPH_RTC
          - RCC_APB1_PERIPH_COMP
          - RCC_APB1_PERIPH_BTIM2
          - RCC_APB1_PERIPH_BTIM1
          - RCC_APB1_PERIPH_GTIM4
          - RCC_APB1_PERIPH_GTIM3
          - RCC_APB1_PERIPH_GTIM2
          - RCC_APB1_PERIPH_GTIM1
return none.

void RCC_EnableAPB2PeriphReset(uint32_t APB2_periph)High Speed APB2 peripheral reset.

Source comment

name    RCC_EnableAPB2PeriphReset.
fun     High Speed APB2 peripheral reset.
param   APB2_periph specifies the APB2 peripheral to reset.
          - RCC_APB2_PERIPH_SPI2
          - RCC_APB2_PERIPH_USART4
          - RCC_APB2_PERIPH_USART1
          - RCC_APB2_PERIPH_ATIM2
          - RCC_APB2_PERIPH_SPI1
          - RCC_APB2_PERIPH_ATIM1
return none.

void RCC_ConfigAdc1mClk(uint32_t ADC1M_clksrc, uint32_t ADC1M_prescaler)Configures the ADCx 1M clock (ADC1MCLK).

Source comment

name    RCC_ConfigAdc1mClk.
fun     Configures the ADCx 1M clock (ADC1MCLK).
param   ADC1M_clksrc(ADC1M clock source):
          - RCC_ADC1MCLK_SRC_HSI
          - RCC_ADC1MCLK_SRC_HSE
param   ADC1M_prescaler(ADC1M clock prescaler):
          - RCC_ADC1MCLK_DIV1
          - RCC_ADC1MCLK_DIV2
          - RCC_ADC1MCLK_DIV4
          - RCC_ADC1MCLK_DIV6
          - RCC_ADC1MCLK_DIV8
          - RCC_ADC1MCLK_DIV10
          - RCC_ADC1MCLK_DIV12
          - RCC_ADC1MCLK_DIV16
          - RCC_ADC1MCLK_DIV32
return  none

void RCC_ConfigAdcSysclk(uint32_t sclk_prescaler)Configures the ADCSysCLK prescaler.

Source comment

name    RCC_ConfigAdcSysclk.
fun     Configures the ADCSysCLK prescaler.
param   sclk_prescaler(ADCSCLK prescaler):
         - RCC_ADCSYSCLK_DIV1     ADC clock = SYSCLK
         - RCC_ADCSYSCLK_DIV2     ADC clock = SYSCLK/2
         - RCC_ADCSYSCLK_DIV3     ADC clock = SYSCLK/3
         - RCC_ADCSYSCLK_DIV4     ADC clock = SYSCLK/4
         - RCC_ADCSYSCLK_DIV5     ADC clock = SYSCLK/5
         - RCC_ADCSYSCLK_DIV6     ADC clock = SYSCLK/6
         - RCC_ADCSYSCLK_DIV8     ADC clock = SYSCLK/8
         - RCC_ADCSYSCLK_DIV10    ADC clock = SYSCLK/10
         - RCC_ADCSYSCLK_DIV12    ADC clock = SYSCLK/12
         - RCC_ADCSYSCLK_DIV16    ADC clock = SYSCLK/16
         - RCC_ADCSYSCLK_DIV32    ADC clock = SYSCLK/32
         - RCC_ADCSYSCLK_DIV64    ADC clock = SYSCLK/64
return  none

void RCC_ConfigI2SClk(uint32_t i2s_clksrc)Configures the I2S clock source(I2SCLK).

Source comment

name    RCC_ConfigI2SClk.
fun     Configures the I2S clock source(I2SCLK).
param   i2s_clksrc(I2S clock source):
         - RCC_I2S_CLKSEL_SYS
         - RCC_I2S_CLKSEL_IOM
return  none

void RCC_ConfigUsart1Clk(uint32_t usart1_clksrc)Configures the UART1 clock source(UART1CLK).

Source comment

name    RCC_ConfigUsart1Clk.
fun     Configures the UART1 clock source(UART1CLK).
param   usart1_clksrc(UART1 clock source):
         - RCC_USART1_CLKSEL_LSI
         - RCC_USART1_CLKSEL_LSE
         - RCC_USART1_CLKSEL_APB2
return  none

void RCC_ConfigUsart4Clk(uint32_t usart4_clksrc)Configures the UART4 clock source(UART4CLK).

Source comment

name    RCC_ConfigUsart4Clk.
fun     Configures the UART4 clock source(UART4CLK).
param   usart4_clksrc(UART4 clock source):
         - RCC_USART4_CLKSEL_LSI
         - RCC_USART4_CLKSEL_LSE
         - RCC_USART4_CLKSEL_APB2
return  none

void RCC_ConfigRTCClk(uint32_t rtc_clksrc)Configures the RTC clock source(RTCCLK).

Source comment

name    RCC_ConfigRTCClk.
fun     Configures the RTC clock source(RTCCLK).
param   rtc_clksrc(RTC clock source):
         - RCC_RTC_CLKSEL_LSI
         - RCC_RTC_CLKSEL_LSE
         - RCC_RTC_CLKSEL_HSE_DIV128
return  none

void RCC_ConfigLowPowerClk(uint32_t lp_clksrc)Configures the LP clock source(LPCLK).

Source comment

name    RCC_ConfigLowPowerClk.
fun     Configures the LP clock source(LPCLK).
param   lp_clksrc(LP clock source):
         - RCC_LP_CLKSEL_LSI
         - RCC_LP_CLKSEL_LSE
return  none

void RCC_ConfigAtim1Clk(uint32_t atimer1_clksrc)Configures the ATIM1 clock source(ATIM1CLK).

Source comment

name    RCC_ConfigAtim1Clk.
fun     Configures the ATIM1 clock source(ATIM1CLK).
param   atimer1_clksrc(ATIM1 clock source):
         - RCC_ATIM1_CLKSEL_SYS
         - RCC_ATIM1_CLKSEL_AHB
         - RCC_ATIM1_CLKSEL_PLL
return  none

void RCC_ConfigAtim2Clk(uint32_t atimer2_clksrc)Configures the ATIM2 clock source(ATIM2CLK).

Source comment

name    RCC_ConfigAtim2Clk.
fun     Configures the ATIM2 clock source(ATIM2CLK).
param   atimer2_clksrc(ATIM2 clock source):
         - RCC_ATIM2_CLKSEL_SYS
         - RCC_ATIM2_CLKSEL_AHB
         - RCC_ATIM2_CLKSEL_PLL
return  none

void RCC_ConfigGtim1Clk(uint32_t gtimer1_clksrc)Configures the GTIM1 clock source(GTIM1CLK).

Source comment

name    RCC_ConfigGtim1Clk.
fun     Configures the GTIM1 clock source(GTIM1CLK).
param   gtimer1_clksrc(GTIM1 clock source):
         - RCC_GTIM1_CLKSEL_SYS
         - RCC_GTIM1_CLKSEL_AHB
return  none

void RCC_ConfigGtim2Clk(uint32_t gtimer2_clksrc)Configures the GTIM2 clock source(GTIM2CLK).

Source comment

name    RCC_ConfigGtim2Clk.
fun     Configures the GTIM2 clock source(GTIM2CLK).
param   gtimer2_clksrc(GTIM2 clock source):
         - RCC_GTIM2_CLKSEL_SYS
         - RCC_GTIM2_CLKSEL_AHB
return  none

void RCC_ConfigGtim3Clk(uint32_t gtimer3_clksrc)Configures the GTIM3 clock source(GTIM3CLK).

Source comment

name    RCC_ConfigGtim3Clk.
fun     Configures the GTIM3 clock source(GTIM3CLK).
param   gtimer3_clksrc(GTIM3 clock source):
         - RCC_GTIM3_CLKSEL_SYS
         - RCC_GTIM3_CLKSEL_AHB
return  none

void RCC_ConfigGtim4Clk(uint32_t gtimer4_clksrc)Configures the GTIM4 clock source(GTIM4CLK).

Source comment

name    RCC_ConfigGtim4Clk.
fun     Configures the GTIM4 clock source(GTIM4CLK).
param   gtimer4_clksrc(GTIM4 clock source):
         - RCC_GTIM4_CLKSEL_SYS
         - RCC_GTIM4_CLKSEL_AHB
return  none

void RCC_ConfigBtim1Clk(uint32_t btimer1_clksrc)Configures the BTIM1 clock source(BTIM1CLK).

Source comment

name    RCC_ConfigBtim1Clk.
fun     Configures the BTIM1 clock source(BTIM1CLK).
param   btimer1_clksrc(BTIM1 clock source):
         - RCC_BTIM1_CLKSEL_LSI
         - RCC_BTIM1_CLKSEL_LSE
         - RCC_BTIM1_CLKSEL_APB1
return  none

void RCC_ConfigIOFilter(uint32_t ioflitclk_div)Configures the Speed of GPIO filter.

Source comment

name    RCC_ConfigIOFilter.
fun     Configures the Speed of GPIO filter.
param   ioflitclk_div value:
        -0 ~ 0x3F
return  none

void RCC_ConfigATIM1Filter(uint32_t atim1flitclk_div)Configures the Speed of ATIM1 filter.

Source comment

name    RCC_ConfigATIM1Filter.
fun     Configures the Speed of ATIM1 filter.
param   atim1flitclk_div value:
        -0 ~ 0x1F
return  none

void RCC_ConfigATIM2Filter(uint32_t atim2flitclk_div)Configures the Speed of ATIM2 filter.

Source comment

name    RCC_ConfigATIM2Filter.
fun     Configures the Speed of ATIM2 filter.
param   atim2flitclk_div value:
        -0 ~ 0x1F
return  none

void RCC_ConfigGTIM1Filter(uint32_t gtim1flitclk_div)Configures the Speed of GTIM1 filter.

Source comment

name    RCC_ConfigGTIM1Filter.
fun     Configures the Speed of GTIM1 filter.
param   gtim1flitclk_div value:
        -0 ~ 0x1F
return  none

void RCC_ConfigGTIM2Filter(uint32_t gtim2flitclk_div)Configures the Speed of GTIM2 filter.

Source comment

name    RCC_ConfigGTIM2Filter.
fun     Configures the Speed of GTIM2 filter.
param   gtim2flitclk_div value:
        -0 ~ 0x1F
return  none

void RCC_ConfigGTIM3Filter(uint32_t gtim3flitclk_div)Configures the Speed of GTIM3 filter.

Source comment

name    RCC_ConfigGTIM3Filter.
fun     Configures the Speed of GTIM3 filter.
param   gtim3flitclk_div value:
        -0 ~ 0x1F
return  none

void RCC_ConfigGTIM4Filter(uint32_t gtim4flitclk_div)Configures the Speed of GTIM4 filter.

Source comment

name    RCC_ConfigGTIM4Filter.
fun     Configures the Speed of GTIM4 filter.
param   gtim4flitclk_div value:
        -0 ~ 0x1F
return  none

void RCC_ConfigMco(uint32_t MCO_source)Selects the clock source to output on MCO pin.

Source comment

name   RCC_ConfigMco.
fun    Selects the clock source to output on MCO pin.
param  MCO_source(clock source to output):
         - RCC_MCO_NOCLK       No clock selected
         - RCC_MCO_LSI         LSI oscillator clock selected
         - RCC_MCO_LSE         LSE oscillator clock selected
         - RCC_MCO_SYSCLK      System clock selected
         - RCC_MCO_HSI         HSI oscillator clock selected
         - RCC_MCO_HSE         HSE oscillator clock selected
         - RCC_MCO_PLLDIV      PLL sysdiv clock selected
return  none.

void RCC_ConfigMcoClkPre(uint32_t MCO_PLL_prescaler)Configures the MCO System and HSI clock prescaler.

Source comment

name    RCC_ConfigMcoClkPre.
fun     Configures the MCO System and HSI clock prescaler.
param   MCO_PLL_prescaler specifies the MCO PLL clock prescaler.
        This parameter can be on of the following values:
          - RCC_MCO_CLK_DIV1
          - RCC_MCO_CLK_DIV2
          - RCC_MCO_CLK_DIV4
          - RCC_MCO_CLK_DIV8
          - RCC_MCO_CLK_DIV16
return  none.

void RCC_EnableHSEClockSecuritySystem(FunctionalState Cmd)Enables the HSE Clock Security System.

Source comment

name    RCC_EnableHSEClockSecuritySystem.
fun     Enables the HSE Clock Security System.
param   Cmd:
          - ENABLE
          - DISABLE
return  none.

void RCC_EnableLSEClockSecuritySystem(FunctionalState Cmd)Enables the LSE Clock Security System.

Source comment

name    RCC_EnableLSEClockSecuritySystem.
fun     Enables the LSE Clock Security System.
param   Cmd:
          - ENABLE
          - DISABLE
return  none.

void RCC_EnableHSECaptureRequest(FunctionalState Cmd)Configure whether to enable HSE Timer Capture requests .

Source comment

name    RCC_EnableHSECaptureRequest.
fun     Configure whether to enable HSE Timer Capture requests .
param   Cmd:
          - ENABLE
          - DISABLE
return  none.

void RCC_EnableLSECaptureRequest(FunctionalState Cmd)Configure whether to enable LSE Timer Capture requests.

Source comment

name    RCC_EnableLSECaptureRequest.
fun     Configure whether to enable LSE Timer Capture requests.
param   Cmd:
          - ENABLE
          - DISABLE
return  none.

void RCC_EnableEMCDetect(uint32_t EMC_type, FunctionalState Cmd)Configure whether to enable EMC detection.

Source comment

name    RCC_EnableEMCDetect.
fun     Configure whether to enable EMC detection.
param   EMC_type:
          - RCC_EMC_GB
          - RCC_EMC_GBN
param   Cmd:
          - ENABLE
          - DISABLE
return  none.

void RCC_ConfigEMCDetectLevel(uint32_t EMC_type, uint8_t level)Configures the voltage threshold detected by the EMC.

Source comment

name    RCC_ConfigEMCDetectLevel.
fun     Configures the voltage threshold detected by the EMC.
param   EMC_type:
          - RCC_EMC_GB
          - RCC_EMC_GBN
param   level (The input parameters must be the following values):
          - 0x0 ~ 0x3
return  none

void RCC_EnableEMCReset(uint32_t EMC_type, FunctionalState Cmd)Configure whether to generate a reset request when an EMC error occurs.

Source comment

name    RCC_EnableEMCReset.
fun     Configure whether to generate a reset request when an EMC error occurs.
param   EMC_type:
          - RCC_EMC_GB
          - RCC_EMC_GBN
param   Cmd:
          - ENABLE
          - DISABLE
return  none.

void RCC_EnableEMCSwitch(uint32_t EMC_type, FunctionalState Cmd)Configure whether to enable EMC switch.

Source comment

name    RCC_EnableEMCSwitch.
fun     Configure whether to enable EMC switch.
param   EMC_type:
          - RCC_EMC_GB
          - RCC_EMC_GBN
param   Cmd:
          - ENABLE
          - DISABLE
return  none.

void RCC_EnableEMCGBInt(FunctionalState Cmd)Configure whether to enable EMC GB.

Source comment

name    RCC_EnableEMCGBInt.
fun     Configure whether to enable EMC GB.
param   Cmd:
          - ENABLE
          - DISABLE
return  none.

void RCC_EnableEMCGBNInt(FunctionalState Cmd)Configure whether to enable EMC GBN int.

Source comment

name    RCC_EnableEMCGBNInt.
fun     Configure whether to enable EMC GBN int.
param   Cmd:
          - ENABLE
          - DISABLE
return  none.

void RCC_EnableGlitchDetect(FunctionalState Cmd)Configure whether to enable Glitch.

Source comment

name    RCC_EnableGlitchDetect.
fun     Configure whether to enable Glitch.
param   Cmd:
          - ENABLE
          - DISABLE
return  none.

void RCC_ConfigGlitchDetectLevel(uint8_t level)Configures the voltage threshold detected by the Glitch.

Source comment

name    RCC_ConfigGlitchDetectLevel.
fun     Configures the voltage threshold detected by the Glitch.
param   level (The input parameters must be the following values):
        - 0x0 ~ 0x1F
return  none

void RCC_EnableGlitchReset(FunctionalState Cmd)Configure whether to enable Glitch reset.

Source comment

name    RCC_EnableGlitchReset.
fun     Configure whether to enable Glitch reset.
param   Cmd:
          - ENABLE
          - DISABLE
return  none.

void RCC_EnableGlitchSwitch(FunctionalState Cmd)Configure whether to enable Glitch switch.

Source comment

name    RCC_EnableGlitchSwitch.
fun     Configure whether to enable Glitch switch.
param   Cmd:
          - ENABLE
          - DISABLE
return  none.

void RCC_EnableGlitchInt(FunctionalState Cmd)Configure whether to enable GLITCH int.

Source comment

name    RCC_EnableGlitchInt.
fun     Configure whether to enable GLITCH int.
param   Cmd:
          - ENABLE
          - DISABLE
return  none.

void RCC_EnableM4LockupReset(FunctionalState Cmd)Configure whether to enable M4 lockup reset.

Source comment

name    RCC_EnableM4LockupReset.
fun     Configure whether to enable M4 lockup reset.
param   Cmd:
          - ENABLE
          - DISABLE
return  none.

void RCC_EnablePwrUpStep(FunctionalState Cmd)Power up step width enable.

Source comment

name    RCC_EnablePwrUpStep.
fun     Power up step width enable.
param   Cmd:
          - ENABLE
          - DISABLE
return  none.

void RCC_EnablePwrDownStep(FunctionalState Cmd)Power down step width enable.

Source comment

name    RCC_EnablePwrDownStep.
fun     Power down step width enable.
param   Cmd:
          - ENABLE
          - DISABLE
return  none.

void RCC_ConfigPwrUpStepWidth(uint32_t pwrupstepwidth)Configure power up step width.

Source comment

name    RCC_ConfigPwrUpStepWidth.
fun     Configure power up step width.
param   pwrupstepwidth (power up step width, 0<pwrupstepwidth<=1023)
return  none

void RCC_ConfigPwrDownStepWidth(uint32_t pwrdownstepwidth)Configure power down step width.

Source comment

name    RCC_ConfigPwrDownStepWidth.
fun     Configure power down step width.
param   pwrdownstepwidth (power down step width, 0<pwrdownstepwidth<=1023)
return  none

void RCC_EnablePStepSf(FunctionalState Cmd)Enable the software power step.

Source comment

name    RCC_EnablePStepSf.
fun     Enable the software power step.
param   Cmd:
          - ENABLE
          - DISABLE
return  none.

void RCC_PStepSfDiv(uint32_t pstepsfdiv)Software-Controlled Power-Saving Stages (Based on PLL Clock)

Source comment

name    RCC_PStepSfDiv.
fun   Software-Controlled Power-Saving Stages (Based on PLL Clock)
param   pstepsfdiv (power saving stage divider based on PLL clock):
         - RCC_PWRUP_PSTEPSFDIV_1
         - RCC_PWRUP_PSTEPSFDIV_2
         - RCC_PWRUP_PSTEPSFDIV_4
         - RCC_PWRUP_PSTEPSFDIV_8
         - RCC_PWRUP_PSTEPSFDIV_16
return  none

void RCC_ClearPwrDownStepFlag(void)Clear pstep downstep flag.

Source comment

name    RCC_ClearPwrDownStepFlag.
fun     Clear pstep downstep flag.
return  none.

FlagStatus RCC_GetPwrDownStepFlag(void)Get PLL Power Step Control down step flag.

Source comment

name    RCC_GetPwrDownStepFlag.
fun     Get PLL Power Step Control down step flag.
return  FlagStatus:
          - SET
          - RESET

uint32_t RCC_GetPwrStepFsm(void)Get PLL Power Step Control FSM.

Source comment

name    RCC_GetPwrStepFsm.
fun     Get PLL Power Step Control FSM.
return  Status:
        0  - START
        1  - UP step1
        3  - UP step2
        7  - UP step3
        15 - UP step4
        14 - STOP
        12 - DOWN step1
        8  - DOWN step2
        9  - DOWN step3
        11 - DOWN step4

void RCC_ConfigInt(uint32_t Interrupt, FunctionalState Cmd)Enables the specified RCC interrupts.

Source comment

name    RCC_ConfigInt.
fun     Enables the specified RCC interrupts.
param   Interrupt(the RCC interrupt sources to be enabled):
         - RCC_ENABLE_LSESSI
         - RCC_ENABLE_PLLRDI
         - RCC_ENABLE_HSERDI
         - RCC_ENABLE_HSIRDI
         - RCC_ENABLE_LSERDI
         - RCC_ENABLE_LSIRDI
param   Cmd:
          - ENABLE
          - DISABLE
return  none

INTStatus RCC_GetIntStatus(uint32_t interrupt_flag)Checks whether the specified RCC interrupt has occurred or not.

Source comment

name    RCC_GetIntStatus.
fun     Checks whether the specified RCC interrupt has occurred or not.
param   interrupt_flag(RCC interrupt source to check):
        -  RCC_INT_LSESSIF    LSE clock security system interrupt flag
        -  RCC_INT_CLKSSIF    HSE clock security system interrupt flag
        -  RCC_INT_PLLRDIF    PLL ready interrupt flag
        -  RCC_INT_HSERDIF    HSE ready interrupt flag
        -  RCC_INT_HSIRDIF    HSI ready interrupt flag
        -  RCC_INT_LSERDIF    LSE ready interrupt flag
        -  RCC_INT_LSIRDIF    LSI ready interrupt flag
return  The new state of RccInt
         - SET
         - RESET

void RCC_ClrIntPendingBit(uint32_t interrupt_clear)Clears the RCC’s interrupt pending bits.

Source comment

name    RCC_ClrIntPendingBit.
fun     Clears the RCC's interrupt pending bits.
param   interrupt_clear specifies the interrupt pending bit to clear.
          -  RCC_CLR_LSESSIF    Clear LSE clock security system interrupt flag
          -  RCC_CLR_CLKSSIF    Clear HSE clock security system interrupt flag
          -  RCC_CLR_PLLRDIF    Clear PLL ready interrupt flag
          -  RCC_CLR_HSERDIF    Clear HSE ready interrupt flag
          -  RCC_CLR_HSIRDIF    Clear HSI ready interrupt flag
          -  RCC_CLR_LSERDIF    Clear LSE ready interrupt flag
          -  RCC_CLR_LSIRDIF    Clear LSI ready interrupt flag
return  none.

Use note: Confirm that the matching status has been read before clearing an interrupt pending bit, so no interrupt event is missed.

FlagStatus RCC_GetFlagStatus(uint8_t RCC_flag)Checks whether the specified RCC flag is set or not.

Source comment

name    RCC_GetFlagStatus.
fun     Checks whether the specified RCC flag is set or not.
param   RCC_flag:
          - RCC_CTRL_FLAG_HSIRDF
          - RCC_CTRL_FLAG_HSERDF
          - RCC_CTRL_FLAG_PLLRDF
          - RCC_CTRL_FLAG_LSIRDF
          - RCC_CTRL_FLAG_LSERDF
          - RCC_CTRLSTS_FLAG_PORRSTF
          - RCC_CTRLSTS_FLAG_PINRSTF
          - RCC_CTRLSTS_FLAG_WWDGRSTF
          - RCC_CTRLSTS_FLAG_SFTRSTF
          - RCC_CTRLSTS_FLAG_IWDGRSTF
          - RCC_CTRLSTS_FLAG_GLITCHRSTF
          - RCC_CTRLSTS_FLAG_EMCGBRSTF
          - RCC_CTRLSTS_FLAG_EMCGBNRSTF
          - RCC_CTRLSTS_FLAG_LKUPRSTF
return  FlagStatus:
          - SET
          - RESET

void RCC_ClearResetFlag(void)Clears the RCC reset flags.

Source comment

name    RCC_ClearResetFlag.
fun     Clears the RCC reset flags.
param   none
return  none
note  Clear the following flags:
          - RCC_CTRLSTS_FLAG_PORRSTF
          - RCC_CTRLSTS_FLAG_PINRSTF
          - RCC_CTRLSTS_FLAG_WWDGRSTF
          - RCC_CTRLSTS_FLAG_SFTRSTF
          - RCC_CTRLSTS_FLAG_IWDGRSTF
          - RCC_CTRLSTS_FLAG_GLITCHRSTF
          - RCC_CTRLSTS_FLAG_EMCGBRSTF
          - RCC_CTRLSTS_FLAG_EMCGBNRSTF
          - RCC_CTRLSTS_FLAG_LKUPRSTF

Use note: Read then clear the reset flag promptly, otherwise the source of the next reset cannot be told apart.

5.17.3 Demo descriptions

This section describes the single RCC example: RCC_ClockConfig switches the system clock to one of the HSI, HSE or PLL sources, prints the resulting clock frequencies over the serial port and outputs the selected clock on the MCO pin.

5.17.3.1 RCC_ClockConfig Clock tree configuration

Example directory: projects/n32g41x_EVAL/examples/RCC/RCC_ClockConfig/

After reset the serial port prints the default clock frequencies→switch the system clock to HSI, HSE or PLL according to the source selected at compile time→reinitialize the serial port and print the SYSCLK, HCLK, PCLK1 and PCLK2 frequencies→configure PA8 as the MCO alternate output and select the divider→the main loop spins waiting for measurement

Item	Source analysis
Function	Switch the system clock (SYSCLK) to one of the HSI, HSE or PLL sources, print the SYSCLK, HCLK, PCLK1 and PCLK2 frequencies over the serial port after the switch, and output the selected clock on the MCO pin PA8.
Source files	`src/main.c`: `main`, `PrintfClockInfo`, `MCO_Configuration` and `SetSysClockToHSI`, `SetSysClockToHSE`, `SetSysClockToPLL`; `inc/main.h`: clock source selection and MCO pin macros; `src/n32g41x_it.c`, `inc/n32g41x_it.h`: interrupt service routines; `readme.txt`: function, environment and usage notes; `MDK-ARM/`, `EWARM/`: Keil and IAR projects. Serial logging comes from `bsp/src/log.c` and the millisecond delay from `bsp/src/delay.c`.
Key configuration	Clock source: selected by `SYSCLK_SOURCE_SELECT`, default `SYSCLK_SOURCE_PLL`; HSI 16 MHz, HSE 8 MHz, PLL calls `SetSysClockToPLL(RCC_PLL_SRC_HSE, 72000000U)` with `pllinpre` 2, `pllmul` 36, `plloutdiv` `RCC_PLL_OD_DIV_1` and `pllsysdiv` ENABLE, giving SYSCLK 72 MHz and PCLK1 36 MHz; MCO: pin PA8 (`GPIO_PIN_8`, `GPIOA`), `GPIO_AF7` on the N32G412 and `GPIO_AF13` on the N32G415, divider `RCC_MCO_CLK_DIV2` (HSI), `RCC_MCO_CLK_DIV1` (HSE) and `RCC_MCO_CLK_DIV8` (PLL); Serial: TX PA9 at 115200.
Program and data path	`main` calls `PrintfClockInfo("After reset")` to print the reset clock, then calls `SetSysClockToHSI`, `SetSysClockToHSE` or `SetSysClockToPLL` according to `SYSCLK_SOURCE_SELECT` to reconfigure the clock and the bus prescalers, printing `Clock configuration failure!` if it fails; then `PrintfClockInfo` prints the new frequencies and `MCO_Configuration` enables the GPIO clock, configures PA8 as an alternate push-pull output and sets the MCO divider and clock source, and enters an empty `while(1)`.
Main APIs	`RCC_DeInit`, `RCC_EnableHsi`, `RCC_ConfigHse`, `RCC_ConfigPll`, `RCC_EnablePll`, `RCC_EnablePllSysclkDiv`, `RCC_ConfigHclk`, `RCC_ConfigPclk1`, `RCC_ConfigPclk2`, `RCC_ConfigSysclk`, `RCC_GetSysclkSrc`, `RCC_GetClocksFreqValue`, `RCC_ConfigMco`, `RCC_ConfigMcoClkPre`
Verification	After a reset the serial port first prints `After reset` and the default clock, then prints the clock information of the selected mode (in the PLL mode `HSE->PLL->SYSCLK, 72MHz` together with the SYSCLK, HCLK, PCLK1 and PCLK2 values); measure PA8 with an oscilloscope: 8 MHz in the HSI mode, 8 MHz in the HSE mode and 9 MHz in the PLL mode.
Use note	Supports N32G412x8L7, N32G412xBL7, N32G415x8L7 and N32G415xBL7; the development environment is KEIL MDK-ARM V5.34 or IAR EWARM 8.50.1. Change `SYSCLK_SOURCE_SELECT` in `inc/main.h` before switching the clock source; the PLL mode requires `HSE_VALUE` to be 8 MHz; the source comment requires the MCO output not to exceed 20 MHz.

Core-code walkthrough and porting

The example selects the clock source and MCO pin with header macros, reconfigures the clock and the bus prescalers along the HSI, HSE or PLL path, and finally prints the frequencies and outputs the MCO on PA8.

Data path: SYSCLK_SOURCE_SELECT (inc/main.h) -> SetSysClockToHSI/SetSysClockToHSE/SetSysClockToPLL configure the clock source, the PLL and the bus prescalers -> RCC_ConfigSysclk switches the system clock -> RCC_GetClocksFreqValue -> PrintfClockInfo prints over the serial port -> MCO_Configuration configures PA8 as the alternate output

1. Centralize the clock source and MCO settings in header macros. inc/main.h uses SYSCLK_SOURCE_SELECT to choose among the HSI, HSE and PLL clock sources, and a group of macros to give the port, pin number and alternate function of the MCO pin.

inc/main.hinc/main.h

/* System clock source selection */
#define SYSCLK_SOURCE_HSI         0
#define SYSCLK_SOURCE_HSE         1
#define SYSCLK_SOURCE_PLL         2

#ifndef SYSCLK_SOURCE_SELECT
#define SYSCLK_SOURCE_SELECT      SYSCLK_SOURCE_PLL  /* Select sysclk source */
#endif

/* MCO pin definition: PA8 */
#define MCO_PIN                   GPIO_PIN_8
#define MCO_GPIO                  GPIOA

#if defined(N32G412)
#define MCO_AF                    GPIO_AF7
#elif defined(N32G415)
#define MCO_AF                    GPIO_AF13
#endif

Changing the clock source only requires editing SYSCLK_SOURCE_SELECT; changing the MCO pin or the chip means editing MCO_PIN, MCO_GPIO and MCO_AF, without touching main.c.

2. Look up the PLL parameters and bus prescalers for the target frequency. SetSysClockToPLL looks up SYS_freq in a table that gives the multiplier, output divider, PLLSYSDIV and FLASH latency for each frequency step, and then configures HCLK, PCLK1 and PCLK2 for all paths.

src/main.csrc/main.c · SetSysClockToPLL

    switch (SYS_freq)
    {
        case 72000000:
            /* 4MHz * 36 = 144MHz(FVCO) / 1(PLLOD) /1 = 144MHz(Fpll) */
            latency   = FLASH_LATENCY_1;   /* 36MHz < SYSCLK <= 72MHz */
            pllmul    = 36;
            plloutdiv = RCC_PLL_OD_DIV_1;
            pllsysdiv = ENABLE;
            break;
        case 80000000:
            /* 4MHz * 40 = 160MHz(FVCO) / 2(PLLOD) /1 = 80MHz(Fpll) */
            latency   = FLASH_LATENCY_2;   /* 72MHz < SYSCLK <= 80MHz */
            pllmul    = 40;
            plloutdiv = RCC_PLL_OD_DIV_2;
            pllsysdiv = DISABLE;
            break;
        case 96000000:
            /* 4MHz * 48 = 192MHz(FVCO) / 2(PLLOD) /1 = 96MHz(Fpll) */
            latency   = FLASH_LATENCY_2;   /* 72MHz < SYSCLK <= 96MHz */
            pllmul    = 48;
            plloutdiv = RCC_PLL_OD_DIV_2;
            pllsysdiv = DISABLE;
            break;
        default:
            return ERROR;
    }

src/main.csrc/main.c · SetSysClockToPLL

    /* HCLK = SYSCLK */
    RCC_ConfigHclk(RCC_SYSCLK_DIV1);

    /* PCLK2 = HCLK */
    RCC_ConfigPclk2(RCC_HCLK_DIV1);

    /* PCLK1 = HCLK/2 */
    RCC_ConfigPclk1(RCC_HCLK_DIV2);

The PLL input divider depends on the clock source: 4 for RCC_PLL_SRC_HSI and 2 for RCC_PLL_SRC_HSE; when changing to another system frequency, also check that the FLASH latency and the PCLK1 and PCLK2 dividers stay within the frequency limits of the user manual.

3. Enable the PLL and switch to it as the system clock. After the parameters are written, the code enables the PLL, waits for PLLRDF to be set, sets PLLSYSDIV, then switches SYSCLK to the PLL and waits for the status bit to confirm the switch, counting timeout_value at each step to avoid a dead loop.

src/main.csrc/main.c · SetSysClockToPLL

    /* Configure PLL: source, input prescaler, multiplier, output prescaler */
    RCC_ConfigPll(PLL_src, pllinpre, pllmul, plloutdiv);

    /* Enable PLL */
    RCC_EnablePll(ENABLE);

    /* Wait till PLL is ready */
    while (RCC_GetFlagStatus(RCC_CTRL_FLAG_PLLRDF) != SET)
    {
        if ((timeout_value--) == 0)
        {
            return ERROR;
        }
    }
    
    /* Enable or Disable PLLSYSDIV (SYSCLK = FPLL / pllsysdiv) */
    RCC_EnablePllSysclkDiv(pllsysdiv);

    /* Select PLL as system clock source */
    RCC_ConfigSysclk(RCC_SYSCLK_SRC_PLL);

    /* Wait till PLL is used as system clock source */
    timeout_value = 0xFFFFFFFF;
    while (RCC_GetSysclkSrc() != RCC_SYSCLK_STS_PLL)
    {
        if ((timeout_value--) == 0)
        {
            return ERROR;
        }
    }

RCC_ConfigPll must be called before RCC_EnablePll, and PLLSYSDIV is set only after the PLL is ready; after changing the clock source or the multiplier, confirm that the PLL input frequency, FVCO and output frequency all fall within the ranges given in the user manual.

4. Select the branch in main and print the frequencies. main enters the branch selected by SYSCLK_SOURCE_SELECT and calls the matching clock configuration function; the PLL branch uses the HSE as the source with a 72 MHz target and prints a message on failure, after which PrintfClockInfo reinitializes the serial port and prints the four frequencies.

src/main.csrc/main.c · main

#elif SYSCLK_SOURCE_SELECT == SYSCLK_SOURCE_PLL
    /* Method 3: PLL as system clock (72MHz from HSE) */
    if (SetSysClockToPLL(RCC_PLL_SRC_HSE, 72000000U) == ERROR)
    {
        log_info("Clock configuration failure!\n");
    }
    PrintfClockInfo("HSE->PLL->SYSCLK, 72MHz");

    MCO_Configuration(RCC_MCO_SYSCLK, RCC_MCO_CLK_DIV8);
#endif

src/main.csrc/main.c · PrintfClockInfo

void PrintfClockInfo(const char* msg)
{
    log_init(); /* should reinit after sysclk changed */
    log_info("\n--------------------------------\n");
    log_info("%s:\n", msg);
    RCC_GetClocksFreqValue(&RCC_ClockFreq);
    log_info("SYSCLK: %d\n", RCC_ClockFreq.SysclkFreq);
    log_info("HCLK: %d\n", RCC_ClockFreq.HclkFreq);
    log_info("PCLK1: %d\n", RCC_ClockFreq.Pclk1Freq);
    log_info("PCLK2: %d\n", RCC_ClockFreq.Pclk2Freq);
    SysTick_Delay_Ms(1);/* Waiting for the log transmission to complete */
}

Because the serial baud rate follows the clock, PrintfClockInfo calls log_init to reinitialize the port every time; the PLL branch requires HSE_VALUE to be 8 MHz, since SetSysClockToPLL returns ERROR directly when HSE_VALUE is not 8000000, so change that macro together with the crystal.

5. Output the MCO clock on PA8. MCO_Configuration enables the GPIO clock, configures PA8 as an alternate push-pull output, and then writes the MCO divider and clock source; the three modes output SYSCLK divided by 2, 1 and 8 respectively.

src/main.csrc/main.c · MCO_Configuration

void MCO_Configuration(uint32_t MCO_source, uint32_t MCO_prescaler)
{
    GPIO_InitType GPIO_InitStructure;

    /* Enable GPIO clock */
    RCC_EnableAHBPeriphClk(RCC_AHB_PERIPH_GPIO, ENABLE);

    /* Configure MCO pin as alternate push-pull */
    GPIO_InitStruct(&GPIO_InitStructure);
    GPIO_InitStructure.Pin            = MCO_PIN;
    GPIO_InitStructure.GPIO_Mode      = GPIO_MODE_AF_PP;
    GPIO_InitStructure.GPIO_Pull      = GPIO_NO_PULL;
    GPIO_InitStructure.GPIO_Alternate = MCO_AF;
    GPIO_InitPeripheral(MCO_GPIO, &GPIO_InitStructure);

    /* Configure MCO prescaler */
    RCC_ConfigMcoClkPre(MCO_prescaler);

    /* Select MCO clock source */
    RCC_ConfigMco(MCO_source);
}

The source comment requires the MCO output not to exceed 20 MHz, so whenever the MCO clock source, the divider or the MCO pin is changed, re-check the divider against that limit.

Corresponding source files: src/main.c, inc/main.h

5.17.4 Notes and troubleshooting

Scenario	Check & action	Source
System clock source switching and stop restriction	After reset the system clock defaults to the HSI; a clock source cannot be stopped while it is used, directly or through the PLL, as the system clock. Confirm that the ready flag of the target source is set before switching, since a switch does not happen while the target source is not ready.	User manual
PLL configuration and input clock switching	The PLL clock source, input prescaler, multiplier and output prescaler must be configured before the PLL is enabled and cannot be changed while it is active; when switching the PLL input clock source, make the new source ready before turning off the previous one.	User manual
PLL frequency ranges and SYSCLK limit	When setting the PLL dividers and multiplier, the PLL input frequency and the divided input frequency must both be within 8 MHz to 32 MHz, FVCO within 96 MHz to 160 MHz and the PLL output within 64 MHz to 160 MHz; SYSCLK must not exceed 80 MHz on the N32G412 and 96 MHz on the N32G415.	User manual
ATIM using the PLL clock	When the clock source of ATIM1 or ATIM2 is set to the PLL, make sure the system clock source is also the PLL and that the PLL output does not exceed 144 MHz and SYSCLK does not exceed 72 MHz.	User manual
Bus clock limits	When setting APB2PRES and APB1PRES in `RCC_CFG`, keep PCLK2 within 80 MHz and PCLK1 within 40 MHz on the N32G412, and PCLK2 within 96 MHz and PCLK1 within 48 MHz on the N32G415.	User manual
PLLSYSDIV setting order	Set `RCC_CFG.PLLSYSDIV` to 0 before enabling the PLL, and configure this bit only after the PLL is ready.	User manual
LSE enable and disable timing	Disabling the LSE takes 3 LSE cycles to complete; after re-enabling the LSE, `RCC_CTRL.LSERDF` is set only after 1024 LSE cycles.	User manual
LSE clock security system	Once `RCC_CTRL.LSECSSEN` is enabled, it can only be cleared by a system reset or automatically after an LSE failure is detected.	User manual
Glitch detection enable order	After enabling `RCC_EMCCTRL.GVDET`, wait 10 us or more before enabling `GVRST` and `GVSW`.	User manual

The errata list of the N32G412 and N32G415 series errata sheet V1.0.0 (2026.6.30) contains a single row for the A version chip with an empty errata link column and does not list any specific items.