5.11 IWDG Guide

This chapter describes the file layout, the 9 public functions, and the single IWDG_Reset example of the independent watchdog (IWDG) support in the N32G033 standard peripheral library. Read the “Independent watchdog” chapter of the user manual for the counting sequence, key values, and timeout, and the errata sheet for known chip issues.

5.11.1 Related files

Relative path	Purpose
`firmware/n32g033_std_periph_driver/inc/n32g033_iwdg.h`	Defines the write-protection, status-flag, and prescaler enums, and declares the 9 watchdog configuration, feed, and status functions
`firmware/n32g033_std_periph_driver/src/n32g033_iwdg.c`	Implements those 9 functions: write-protection switch, prescaler and reload setup, reload and start, feeding, status read, debug freeze, and interrupt enable
`projects/n32g033_EVAL/examples/IWDG/`	IWDG example root directory, with 1 example: IWDG_Reset
`projects/n32g033_EVAL/examples/IWDG/IWDG_Reset/`	Project layout of this example: `MDK-ARM/`, `EWARM/`, `inc/`, `src/`, and `readme.txt`
`projects/n32g033_EVAL/bsp/`	Board support files shared by the examples: the SysTick delay in `delay.h` and the UART log interface in `log.h`

5.11.2 API reference

The following 9 public functions are listed in the declaration order of n32g033_iwdg.h in 2 groups; each entry gives a summary and the original comment above the function in n32g033_iwdg.c.

Configuration and start

IWDG_WriteConfig, IWDG_SetPrescalerDiv, IWDG_CntReload, IWDG_ReloadKey, IWDG_Enable

Status, debug freeze, and feeding

IWDG_Freeze_Enable, IWDG_GetStatus, IWDG_INT_Enable, IWDG_Feed

void IWDG_WriteConfig(IWDOG_WRITE_CONFIG IWDG_WriteAccess)Enables or disables write protection to IWDG_PREDIV and IWDG_RELV registers.

Source comment

name    IWDG_WriteConfig.
fun     Enables or disables write protection to IWDG_PREDIV and IWDG_RELV registers.
param   IWDG_WriteAccess
        - IWDG_WRITE_ENABLE
        - IWDG_WRITE_DISABLE
return  none

void IWDG_SetPrescalerDiv(uint8_t IWDG_Prescaler)IWDG_Prescaler specifies the IWDG prescaler value.

Source comment

name    IWDG_SetPrescalerDiv.
fun     IWDG_Prescaler specifies the IWDG prescaler value.
param   IWDG_Prescaler :
          - IWDG_PRESCALER_DIV4
          - IWDG_PRESCALER_DIV8
          - IWDG_PRESCALER_DIV16
          - IWDG_PRESCALER_DIV32
          - IWDG_PRESCALER_DIV64
          - IWDG_PRESCALER_DIV128
          - IWDG_PRESCALER_DIV256
return  none

void IWDG_CntReload(uint16_t Reload)Sets IWDG reload value.

Source comment

name    IWDG_CntReload.
fun     Sets IWDG reload value.
param   Reload :
          -0x000 ~ 0x3FFF
return  none

void IWDG_ReloadKey(void)Reload IWDG counter with value defined in IWDG_RELV register.

Source comment

name    IWDG_ReloadKey.
fun     Reload IWDG counter with value defined in IWDG_RELV register.
param   none
return  none

void IWDG_Enable(void)Start watch dog counter.

Source comment

name    IWDG_Enable.
fun     Start watch dog counter.
param   none
return  none

void IWDG_Freeze_Enable(FunctionalState Cmd)Enter or exit IWDG freeze mode.

Source comment

name    IWDG_Freeze_Enable.
fun     Enter or exit IWDG freeze mode.
param  Cmd :
          - ENABLE
          - DISABLE
return  none

FlagStatus IWDG_GetStatus(IWDG_STATUS_FLAG IWDG_FLAG)Checks whether the specified IWDG flag is set or not.

Source comment

name    IWDG_GetStatus.
fun     Checks whether the specified IWDG flag is set or not.
param   IWDG_FLAG :
          - IWDG_PVU_FLAG
          - IWDG_CRVU_FLAG
          - IWDG_FREE_FLAG
return  FlagStatus :
          - RESET
          - SET

void IWDG_INT_Enable(FunctionalState Cmd)Enables or disables the specified IWDG interrupt

Source comment

name    IWDG_INT_Enable.
fun     Enables or disables the specified IWDG interrupt
param  Cmd :
          - ENABLE
          - DISABLE
return  none

void IWDG_Feed(void)Feed IWDG in case reset occur.

Source comment

name    IWDG_Feed
fun     Feed IWDG in case reset occur.
param   none
return  none

5.11.3 Demo descriptions

This section describes the single IWDG example: IWDG_Reset feeds the watchdog periodically to keep the system running, and uses the reset flag and the LEDs to indicate whether an IWDG reset occurred.

5.11.3.1 IWDG_Reset Watchdog reset

Example directory: projects/n32g033_EVAL/examples/IWDG/IWDG_Reset/

Enable the PWR and GPIO clocks→Read the reset flag to tell a watchdog reset from a power-on reset→Set the prescaler and reload value and start the watchdog→Toggle the LED and feed the watchdog from the main loop

Item	Source analysis
Function	Feeds the watchdog periodically to keep running after power-up, and uses LED1 together with the UART log to indicate the reset source after an IWDG timeout.
Source files	`src/main.c` holds the four LED helpers `LedInit`, `LedOn`, `LedOff`, and `LedBlink` plus the watchdog configuration and main loop; `src/n32g033_it.c` provides the Cortex-M0 exception handler skeletons; `inc/main.h` pulls in the peripheral and board headers; `readme.txt` gives the configuration and test steps; the project files are in `MDK-ARM/` and `EWARM/`.
Key configuration	Clock source LSI at about 32 kHz; prescaler 32 and reload value `LsiFreq/128`, a timeout of about 250 ms; LED1 on PA6 and LED2 on PA7, both push-pull outputs; UART: 115200 baud, TX PA9 and RX PA10.
Program and data path	`main` -> `log_init` sets up the UART -> `LedInit` configures the LED pins -> the PWR clock is enabled -> `RCC_CTRLSTS_FLAG_IWDGRSTF` selects the reset source and lights or clears LED1 -> `IWDG_WriteConfig` opens write access -> `IWDG_SetPrescalerDiv` sets the prescaler -> `IWDG_CntReload` sets the reload value -> `IWDG_ReloadKey` -> `IWDG_Enable` -> the main loop toggles LED2, waits 249 ms, and feeds the watchdog with `IWDG_ReloadKey`.
Main APIs	`IWDG_WriteConfig`, `IWDG_SetPrescalerDiv`, `IWDG_CntReload`, `IWDG_ReloadKey`, `IWDG_Enable`
Verification	Compile, download, and power up; LED2 keeps flashing, which means the watchdog is fed normally; change the `SysTick_Delay_Ms` argument to 251 or more and the system keeps resetting with LED1 lit.
Use note	The development environment is KEIL MDK-ARM V5.34.0.0 or IAR EWARM 8.50.1 on the N32G033K8Q7-1_STB V1.0 evaluation board; the system clock is 64 MHz.

Core-code walkthrough and porting

The example computes a timeout from the prescaler and reload value, then feeds the watchdog within 250 ms; once the feed interval exceeds the timeout, a reset occurs.

Data path: IWDG_WriteConfig opens write access → IWDG_SetPrescalerDiv selects LSI/32 → IWDG_CntReload loads LsiFreq/128 → IWDG_ReloadKey reloads the counter → IWDG_Enable starts the watchdog → the main loop toggles LED2 and feeds the watchdog

1. The setup opens write protection, then sets the prescaler and reload value. The prescaler 32 and the reload LsiFreq/128 together give a timeout of about 250 ms.

src/main.csrc/main.c · main

    /* IWDG timeout equal to 250 ms (the timeout may varies due to LSI frequency
       dispersion) */
    /* Enable write access to IWDG_PR and IWDG_RLR registers */
    IWDG_WriteConfig(IWDG_WRITE_ENABLE);

    /* IWDG counter clock: LSI/32 */
    IWDG_SetPrescalerDiv(IWDG_PRESCALER_DIV32);

    /* Set counter reload value to obtain 250ms IWDG TimeOut.
       Counter Reload Value = 250ms/IWDG counter clock period
                            = 250ms / (LSI/128)
                            = 0.25s / (LsiFreq/32)
                            = LsiFreq/(32 * 4)
                            = LsiFreq/128 */
    log_debug("LsiFreq is: %d\n", LsiFreq);

    IWDG_CntReload(LsiFreq / 128);

The timeout varies with the LSI frequency dispersion, so recompute the reload value from the actual LSI frequency and the required worst-case response time when porting.

2. The reset flag tells a watchdog reset from a power-on reset. On an IWDGRSTF match, LED1 is lit and a log line is printed, and the flag is then cleared.

src/main.csrc/main.c · main

    /* Check if the system has resumed from IWDG reset */
    if(RCC_GetFlagStatus(RCC_CTRLSTS_FLAG_IWDGRSTF) != RESET)
    {
        /* IWDGRST flag set */
        /* Turn on LED1 */
        LedOn(LED1_GPIO_PORT, LED1_GPIO_PIN);
        log_info("reset by IWDG\n");
        /* Clear reset flags */
        RCC_ClearResetFlag();
    }
    else
    {
        /* IWDGRST flag is not set */
        /* Turn off LED1 */
        LedOff(LED1_GPIO_PORT, LED1_GPIO_PIN);
    }

The clear must follow the test, otherwise a later power-up cannot identify the watchdog reset again.

3. The main loop feeds the watchdog to keep the counter from overflowing. Each feed follows a 249 ms delay, slightly shorter than the 250 ms timeout.

src/main.csrc/main.c · main

    while(1)
    {
        /* Toggle LED2 */
        LedBlink(LED2_GPIO_PORT, LED2_GPIO_PIN);
        /* Insert 249 ms delay */
        SysTick_Delay_Ms(249);

        /* Reload IWDG counter */
        IWDG_ReloadKey();
    }

Once the feed interval exceeds the timeout a reset occurs, LED1 lights, and the reset flag can be read back.

Corresponding source files: src/main.c, inc/main.h, firmware/n32g033_std_periph_driver/inc/n32g033_iwdg.h

5.11.4 Notes and troubleshooting

Scenario	Check & action	Source
Enable the PWR clock before starting the watchdog	The Independent watchdog chapter of the user manual states that the watchdog reset function is controlled by PWR_CTRL.IWDGRSTEN, and that the counter still counts but no reset occurs while that bit is 0; enable the PWR clock and confirm the bit is 1 before use.	User manual
Unlock and wait for the update before changing the prescaler and reload value	The Independent watchdog chapter of the user manual states that you must write 0x5555 to IWDG_KEY to release write protection, and that the new values must be written only after both PVU and CRVU in IWDG_STS read 0; otherwise the update does not take effect.	User manual
Key values for feeding and starting	The Independent watchdog chapter of the user manual gives the key values: writing 0xAAAA to IWDG_KEY reloads the counter and writing 0xCCCC starts the watchdog; any other value triggers neither action.	User manual
Watchdog interrupt and feeding	The Independent watchdog chapter of the user manual states that an interrupt is entered when the counter value is less than or equal to half the reload value, and that feeding exits the interrupt; without that handling the counter reaches 0 and resets the chip.	User manual

Errata sheet V1.0.0 (2025.9.25) covers revision A silicon and lists no IWDG entries.