AI FAE Platform2. Product and Kit Overview
The N32G033 series is a general-purpose MCU family from Nations Technologies built on a 32-bit Arm Cortex-M0 core, integrating several high-performance analog blocks together with UART, SPI, and I2C interfaces. The applications listed on the website include two-wheel electric vehicles, power tools, self-balancing scooters, outdoor LED displays, BMS, home appliances, oximeters, and appliance control panels.
2.1 Core and Peripheral Overview
The table below lists the maximum resource configuration of the N32G033 series from the “main features” section of the official model page; the bus clock limits come from the “Memory and bus architecture” chapter of the user manual, and the GPIO grouping from the “GPIO and AFIO” chapter.
| Item | Configuration |
|---|---|
| Core | 32-bit Arm Cortex-M0 with single-cycle hardware multiplication |
| Max frequency | 64 MHz |
| Bus clock limit | AHB 64 MHz, APB 32 MHz |
| Memory | Up to 64 KB Flash and 6 KB SRAM; SRAM retains data in Stop mode |
| GPIO | Up to 29, split into GPIOA (16), GPIOB (9), and GPIOF (4) |
| Analog | One 12-bit 1 Msps ADC with up to 11 external input channels; three rail-to-rail OPAMPs with programmable gain; one high-speed analog comparator with a built-in 256-level adjustable reference; built-in NTC temperature detection and an independent reference voltage source |
| Communication | Three UART interfaces up to 4 Mbps; two SPI interfaces up to 16 MHz; two I2C interfaces up to 1 MHz |
| Timers | One 16-bit advanced timer with complementary PWM output; one 16-bit general-purpose timer; one 32-bit general-purpose timer; one 32-bit basic timer with low-power wakeup; one independent watchdog (IWDG) |
| Other peripherals | Three-channel DMA controller; hardware divider and square-root accelerator |
| Reset and supply monitoring | Power-on reset (POR), power-down reset (PDR), and external pin reset; programmable voltage detector (PVD) whose event is routed to EXTI line 7; watchdog reset |
| Debug and boot | SWD debug with PA13 as SWDIO and PA14 as SWCLK; boot mode selected by the BOOT0 pin and user option bytes, among main Flash, system memory, and SRAM |
| Security and identification | Multi-level read protection RDP L0/L1/L2; write protection (WRP); 96-bit UID and 128-bit UCID |
| Operating conditions | 2.0 V to 5.5 V; -40 ℃ to +105 ℃ |
The table above is the maximum configuration of the series. The Flash and SRAM size, the GPIO count, and the peripheral set of a specific part are defined by its datasheet. The system clock defaults to the internal HSI RC oscillator at up to 64 MHz; when you change the divider, make sure the APB clock does not exceed 32 MHz.
2.2 SDK at a Glance
Nsing.N32G033_Library.1.3.0 consists of CMSIS device support files, the standard peripheral driver library, middleware, and evaluation board projects, with the following scale:
- 18 driver modules
- 467 public APIs
- 19 example categories
- 68 examples
| Component | Content |
|---|---|
| Standard peripheral driver library | Each driver module is a pair of .h / .c files;the public API is every function declared in the header |
| CMSIS device support | Device header, system clock initialization, Keil / IAR / GCC startup files, and the GCC linker script |
| Example projects | Organized by peripheral category; every example provides both a Keil MDK-ARM and an IAR EWARM project |
| Application projects | ClassB_demo (Keil and IAR projects), JumpToBOOT (Keil project), and GCC_demo (GCC Makefile project) |
| Middleware | FreeRTOS kernel and the N32 self-test library N32_SelfTest_Library |
| Board support | Debug UART log output and SysTick delay |
The example count covers example entries that contain an MDK-ARM, EWARM, or GCC build project: paired sub-projects that each carry their own readme are counted separately (for example the master and slave projects under UART/LIN), while shared code directories without a project are not counted. The Cortex-M0 and FreeRTOS example categories have no corresponding standard peripheral driver module, and the DBG driver module has no standalone example.
The default system clock source in system_n32g033.c is HSI (the internal 64 MHz RC oscillator), producing 64 MHz by default; before compiling you can change it to 64 MHz, 32 MHz, or 32 kHz through the SYSCLK_FREQ macro, and any other value causes a compile error.